IP Library Granted Patent US 12,640,681
Granted Patent B2
US 12,640,681 · App. 18/978,742 · Granted May 26, 2026

Circuit for performing exponential temperature compensation in an oscillator

Inventors: Shubham Raj Singh (Suwon-si, KR); Subodh Prakash Taigor (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H03B5/04
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Quick Facts
Patent No.
US 12,640,681
App. No.
18/978,742
Granted
May 26, 2026
Kind
B2
Abstract

There is provided an error compensation circuit for eliminating temperature-based frequency error in an oscillator. The error compensation circuit includes a current limiting circuit including a first metal-oxide-semiconductor (MOS) device and a first resistive element connected to the first MOS device, a current generation circuit including a second MOS device and a second resistive element connected in series with the second MOS device, and a p-channel-metal-oxide-semiconductor (PMOS) current mirror configured to output the compensation current to a capacitor of the oscillator. The current limiting circuit is configured to turn off the first MOS device to provide zero compensation current at a first temperature lower than a first reference value, and the current generation circuit is configured to generate a compensation current at a second temperature higher than a second reference value.

Claims (43)

1 . An error compensation circuit for eliminating temperature-based frequency error in an oscillator, comprising:

a current limiting circuit comprising a first metal-oxide-semiconductor (MOS) device and a first resistive element connected to the first MOS device, the current limiting circuit configured to turn off the first MOS device to provide zero compensation current at a first temperature lower than a first reference value;

a current generation circuit comprising a second MOS device, which is a source follower MOS device, and a second resistive element, which is a degeneration resistor, connected in series with the second MOS device, the current generation circuit configured to generate a compensation current at a second temperature higher than a second reference value; and

a p-channel-metal-oxide-semiconductor (PMOS) current mirror configured to output the compensation current to a capacitor of the oscillator.

2 . The error compensation circuit as claimed in claim 1 , wherein the first MOS device comprises a first transistor, and the first resistive element comprises a first resistor and a second resistor.

3 . The error compensation circuit as claimed in claim 2 , wherein the current limiting circuit is configured to:

receive a highly proportional-to-absolute-temperature (PTAT) voltage at a gate of by the first transistor, and

wherein the first transistor remains turned off at temperatures below the first reference value, and acts as a resistor at temperatures higher than the second reference value.

4 . The error compensation circuit as claimed in claim 1 , wherein the current generation circuit comprises a second transistor, a third resistor, a fourth resistor and a diode, and

wherein the second resistive element is the third resistor and the second transistor is the second MOS device.

5 . The error compensation circuit as claimed in claim 4 , wherein a gate of the second transistor is configured to:

receive one of a slightly proportional-to-absolute-temperature (PTAT) voltage, and a complimentary to absolute temperature (CTAT) voltage, and

output a compensation current I comp based on the one of the PTAT voltage and the CTAT voltage.

6 . The error compensation circuit as claimed in claim 5 , wherein the compensation current is generated for compensating a comparator delay variation based on the following equation:

I

c

o

m

p

=

(

V

B

-

V

GS

M

2

)

/

R

1

,

wherein I comp is the compensation current, V B is one of the PTAT voltage and CTAT voltage, VGS M2 is a gate voltage of the second transistor, and R 1 is a resistance value of the third resistor.

7 . The error compensation circuit as claimed in claim 1 , wherein the current generation circuit is configured to generate an exponential current output with respect to range of temperatures higher than the second reference value based on the compensation current.

8 . The error compensation circuit as claimed in claim 1 , wherein a predetermined current is output to the capacitor of the oscillator at the second temperature.

9 . The error compensation circuit as claimed in claim 1 , wherein the first reference value and the second reference value are same.

10 . The error compensation circuit as claimed in claim 1 , wherein the first reference value and the second reference value are different.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2024
From: SINGH, SHUBHAM RAJ; TAIGOR, SUBODH PRAKASH
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 069570/0979 →
Priority Claims (1)
IN 202441062820 · Aug 20, 2024 · national
Continuity (1)
Related Publication 20260058603A1 · Feb 26, 2026
References Cited (6)
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CN 103248319B · 2016 [cited by applicant]
Cimbili, B. et al., “A PVT-tolerant relaxation oscillator in 65nm CMOS”, 2016 IEEE Region 10 Conference (TENCON), Nov. 22-25, 2016, pp. 2315-2318. (5 pages total). [cited by applicant]