IP Library Granted Patent US 12,640,941
Granted Patent B2
US 12,640,941 · App. 17/873,252 · Granted May 26, 2026

Systems and methods for providing reliable physically unclonable functions

Inventors: Shih-Lien Linus Lu (Hsinchu, TW); Cheng-En Lee (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company Limited
H04L9/3278G06F21/73H04L9/0866H04L9/12H10D84/856H10D84/925
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Quick Facts
Patent No.
US 12,640,941
App. No.
17/873,252
Granted
May 26, 2026
Kind
B2
Abstract

Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. A first signal is provided to a first branch of a PUF cell and a second signal is provided to a second branch of the PUF cell, the first and second signals being provided in synchronization. A base PUF cell value is determined based on an output of the PUF cell produced by the first signal and the second signal. A third signal is provided to the first branch and a fourth signal is provided to the second branch, the third signal and fourth signal being provided out of synchronization. A stressed PUF cell value is determined based on an output of the PUF cell produced by the third signal and the fourth signal. The PUF cell is determined to be unusable based on a difference between the PUF cell value and the stressed PUF cell value.

Claims (36)

1 . A method of determining a reliability of a physically unclonable function (PUF) cell of a device that provides an output on a set of two bit lines, comprising:

providing a first signal to a first branch which corresponds to a first word line of the PUF cell and a second signal to a second branch which corresponds to a second word line of the PUF cell, the first signal and the second signal being substantially identical signals and provided in synchronization to gate terminals of the first and second branches respectively;

determining a base PUF cell value based on an output of the PUF cell produced by the first signal and the second signal, wherein the output is based on a voltage difference between the two bit lines; and

determining that the PUF cell is unusable based on the base PUF cell value.

2 . The method of claim 1 , wherein the method further comprises:

providing a third signal to the first branch and a fourth signal to the second branch, the third signal and the fourth signal being spaced in time by a first predetermined amount; and

determining a first stressed PUF cell value based on an output of the PUF cell produced by the third signal and the fourth signal.

3 . The method of claim 2 , further comprising determining that the PUF cell is unusable based on a difference between the base PUF cell value and the first stressed PUF cell value.

4 . The method of claim 1 , further comprising repeating said providing first and second signals and determining a base PUF cell value for a plurality of additional PUF cells to determine additional unusable PUF cells.

5 . The method of claim 1 , further comprising storing a mask in a computer-readable memory that identifies PUF cells of the device that are unusable based on reliability determinations.

6 . The method of claim 5 , further comprising:

determining a device signature based on usable PUF cells using the mask; and

transmitting the device signature from the device using a secure channel.

7 . The method of claim 6 , further comprising:

providing a first operational signal to the first branch of the PUF cell and a second operational signal to the second branch of the PUF cell, the first and second operation signals being provided in synchronization; and

determining an operational PUF cell value based on an output of the PUF cell produced by the first operational signal and the second operational signal, wherein the operational PUF cell value is used as a component of a signature of the device in operation.

8 . The method of claim 1 , wherein the PUF cell comprises two substantially similar transistors, one associated with the first branch and one associated with the second branch, each transistor controlling a voltage of the respective bit line, and one terminal of each of the transistors is connected to a ground node or a source node.

9 . The method of claim 8 , wherein determining the base PUF cell value comprises amplifying the voltage difference between the bit lines.

10 . The method of claim 8 , further comprising pre-charging or predischarging the bit lines prior to providing the first signal and the second signal.

11 . The method of claim 1 , further comprising determining a number of unusable PUF cells associated with the device, wherein the device is classified or rejected based on the number of unusable PUF cells.

12 . A device configured to provide a physically unclonable function (PUF) value, comprising:

a first transistor having a gate controlled by a first control line which corresponds to a first word line of the PUF cell, a first terminal connected to a first bit line, and a second terminal connected to a common node;

a second transistor having a gate controlled by a second control line which corresponds to a second word line of the PUF cell, a first terminal connected to a second bit line, and a second terminal connected to the second terminal of the first transistor; and

a sense amplifier configured to determine a voltage difference between the first and second bit lines to determine a PUF cell value, whereby a first signal of the first control line and a second signal of the second control line are substantially identical signals and provided in synchronization to the gates of the first and second transistors respectively.

13 . The device of claim 12 , wherein the first control line and the second control line are connected to a plurality of PUF cells for simultaneous control of the plurality of PUF cells.

14 . The device of claim 12 , further comprising a control signal generator configured to provide signals to the first control line and the second control line in series to identify unusable cells based on PUF cell value changes, wherein the control signal generator comprises a first multiplexer for selecting a delay for a signal on the first control line and a second multiplexer for selecting a delay for a signal on the second control line.

15 . The device of claim 14 , wherein the control signal generator is further configured to control the PUF cells to determine whether PUF cell values changed when signals are provided to the first control line and the second control lines with different amounts of asynchronous time spacing.

16 . The device of claim 14 , wherein the first transistor and the second transistor are NMOS transistors, wherein the common node is a ground node, wherein the device further comprises a precharging circuit, the precharging circuit configured to charge the first and second bit lines before the control signal generator provides signals to the first control line and the second control line to begin discharging the first and second bit lines via the NMOS transistors.

17 . The device of claim 14 , wherein the first transistor and the second transistor are PMOS transistors, wherein the common node is a source node, wherein the device further comprises a predischarging circuit, the predischarging circuit configured to discharge the first and second bit lines before the control signal generator provides signals to the first control line and the second control line to begin charging the first and second bit lines via the PMOS transistors.

18 . A device comprising:

a control signal generator configured to provide a first signal to a first gate terminal of a first branch of a physically unclonable function (PUF) cell and a second signal to a second gate terminal of a second branch of the PUF cell, wherein the first and second signals are substantially identical signals and provided in synchronization, and the first branch corresponds to a first word line of the PUF cell and the second branch corresponds to a second word line of the PUF cell; and

a PUF strength analyzer configured to determine a base PUF cell value based on an output of the PUF cell produced by the first signal and the second signal and to determine that the PUF cell is unusable based on the base PUF cell value, wherein the output is based on a voltage difference between two bit lines coupled to the PUF cell.

19 . The device of claim 18 , wherein the control signal generator is further configured to provide a third signal to the first branch and a fourth signal to the second branch out of synchronization and the PUF strength analyzer is further configured:

to determine a stressed PUF cell value based on an output of the PUF cell produced by the third signal and the fourth signal; and

to determine that the PUF cell is unusable based on a difference between the base PUF cell value and the stressed PUF cell value.

20 . The method of claim 1 , wherein the first signal and the second signal transition from a logic low level to a logic high level substantially simultaneously.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2022
From: LU, SHIH-LIEN LINUS; LEE, CHENG-EN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 060918/0254 →
Continuity (2)
Continuation 16785878 · Feb 10, 2020
Related Publication 20220360456A1 · Nov 10, 2022
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