IP Library Granted Patent US 12,643,126
Granted Patent B2
US 12,643,126 · App. 18/566,775 · Granted Jun 2, 2026

Electrical crosstalk reduction for a capacitive micromachined ultrasonic transducer array

Inventors: Baris Bayram (Ankara, AR); Berkay Karacaer (Ankara, AR)
Assignee: ORTA DOGU TEKNIK UNIVERSITESI
B06B1/0292A61B8/4488B06B2201/76
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Quick Facts
Patent No.
US 12,643,126
App. No.
18/566,775
Granted
Jun 2, 2026
Kind
B2
Abstract

A novel capacitive micromachined ultrasonic transducer (CMUT) array is provided and the CMUT array employs an additional electrically-addressable conductive shield that isolates each array element individually, hence the novel array is coined as Faraday Caged CMUT array. The state of this conductive shield corresponding to each array element can be set as floating for reduced parasitic and cross-coupling capacitance or grounded for reduced electrical crosstalk. Perpetual, reliable operation in floating state without the risk of catastrophic dielectric electric field breakdown event is enabled by the self-discharging mechanism through diamond emitters featuring high field emission efficiency and acting as lightning rods in a cavity. The lightning rod structure features a movable diamond membrane, which deflects towards the diamond emitter due to electrostatic force (acting as a charge-controlled capacitive device) closing the gap to facilitate the safe intermittent discharging.

Claims (37)

1 . A capacitive micromachined ultrasonic transducer (CMUT) array comprising:

a) at least two array elements, wherein each of the at least two array elements features a plurality of CMUT cells and a single lightning rod structure,

b) each of the plurality of CMUT cells having a top-to-bottom stack of a top electrode conductor, a membrane, a vacuum cavity, a first insulation dielectric layer, a bottom electrode conductor, a second insulation dielectric layer, a Faraday cage electrode conductor, a third insulation layer and a substrate, wherein the Faraday cage electrode conductor is electrically isolated from the bottom electrode conductor and the substrate by the first insulation dielectric layer and the third insulation dielectric layer, respectively,

c) each of the lightning rod structures having a top-to-bottom stack of a grounded electrode conductor, a conductive diamond membrane, a cavity, a conductive diamond emitter and the Faraday cage electrode conductor of the array element.

2 . The CMUT array according to claim 1 , wherein

a) the Faraday cage electrode conductor is conductive and common to the plurality of CMUT cells and the lightning rod structure of the array element, and the Faraday cage electrode conductor is electrically isolated from Faraday cage electrode conductors of other array elements,

b) the Faraday cage electrode conductor is selectively connectable to grounded state and selectively disconnect-able from ground to define a floating state,

c) the Faraday cage electrode conductor is unique to the array element, and the Faraday cage electrode conductor is fully isolated from Faraday cage electrode conductors of the other array elements,

wherein for M array elements there are M corresponding Faraday cage electrode conductors, and the M corresponding Faraday cage electrode conductors are isolated from each other,

d) the grounded state of the Faraday cage electrode suppresses an effect of the substrate on a bottom electrode and reduces electrical crosstalk between neighboring array elements,

e) the floating state of the Faraday cage electrode reduces a parasitic capacitance of the array element and a cross-coupling capacitance of the array element and the neighboring array element,

f) the CMUT array is operable such that, during a transmit operation of the array element, the Faraday cage electrode conductor is in the grounded state, and during a receive operation of the array element, the Faraday cage electrode conductor is in the floating state,

g) in the floating state, the Faraday cage electrode conductor accumulates charges in time due to a leakage current through the second insulation dielectric layer as a result of an applied voltage on the bottom electrode.

3 . The CMUT array according to claim 1 , wherein

a) each of the at least two array elements is independently operable, based on whether the array element is operating in the transmit operation or the receive operation, with the unique Faraday cage electrode conductor of the each of the at least two array elements in the grounded state or the floating state regardless of the operational status of the other array elements,

b) CMUT cells are operable in conventional, collapse, resistive-collapse and collapse-snapback modes.

4 . The CMUT array according to claim 1 , wherein the lightning rod structure comprises

a) a movable grounded conductive diamond membrane separated by a gap from the fixed conductive diamond emitter, the movable grounded conductive diamond membrane is electrically connected to ground,

b) the gap is vacuum-sealed or air-filled, wherein pressure in the cavity ranges from atmospheric pressure down to low pressure,

c) a movable membrane, wherein the movable membrane is configured to deflect towards the conductive diamond emitter due to electrostatic force to close the gap to facilitate safe intermittent discharging through the conductive diamond emitter, the lightning rod structure operating as a charge-controlled capacitive device,

d) the conductive diamond emitter having a low work function, a high enhancement factor, and electrical conductivity to enable stable discharging at high emission current density,

e) an insulator layer on a periphery of the conductive diamond membrane providing mechanical support.

5 . A method for microfabrication of the CMUT array according to claim 1 , comprising;

a) performing patterning of a conductive device layer of a silicon-on-insulator (SOI) wafer to construct a Faraday cage of the array element with lithography and deep reactive ion etching (DRIE),

b) performing thermal growth of silicon dioxide to provide electrical isolation of Faraday Cage from the other electrodes of the array element,

c) performing polysilicon layer deposition, comprising the operation of doping and patterning with lithography and reactive ion etching (RIE) to construct a bottom electrode,

d) performing low temperature oxide (LTO) layer deposition, comprising the operation of patterning with lithography and RIE to construct an anchor of the CMUT cell,

e) performing patterning of the thermal grown silicon dioxide with lithography and RIE to provide electrical contact between the Faraday cage and the conductive diamond emitter,

f) performing first boron-doped nanocrystalline diamond (BNCD) layer deposition, comprising the operation of patterning with lithography and RIE (using LTO as hard mask) to form the conductive diamond emitters,

g) performing high temperature oxide (HTO) deposition, comprising the operation of patterning with lithography and RIE to form the first insulation dielectric layer above the bottom electrode,

h) performing polysilicon layer deposition, comprising the operation of doping and patterning with lithography and RIE as a sacrificial layer in an active area of the CMUT cell,

i) performing polysilicon layer deposition, comprising the operation of doping and patterning with lithography and RIE as a sacrificial layer to define etch channels and to construct dimple spacing,

j) performing second BNCD layer deposition, comprising the operation of patterning with lithography and RIE using LTO as hard mask to construct the membrane having dimples of the CMUT cell and the membrane having dimples of the lightning rod structure and to define an etch via for sacrificial etch of polysilicon, an opening for metal pad connections, and a separation zone between membrane of the CMUT cell and membrane of a lightning rod,

k) performing sacrificial etching of polysilicon in XeF 2 plasma,

l) Performing LTO layer deposition to provide sealing of the CMUT cell cavity and lightning rod cavity,

m) performing patterning of silicon dioxide with lithography and buffered hydrofluoric acid (BHF) etching for removal of unnecessary silicon dioxide,

n) performing metallization and patterning of electrode pads with metal lift-off technique.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2023
From: BAYRAM, BARIS; KARACAER, BERKAY
To: ORTA DOGU TEKNIK UNIVERSITESI
Reel/Frame 065759/0144 →
Continuity (1)
Related Publication 20240286171A1 · Aug 29, 2024
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