3D package for semiconductor thermal management
A 3D package for semiconductor thermal management can include a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept cooling liquid therethrough, a first tubular connection for providing cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel. Integrated slots can be provided for accepting and mounting semiconductor components. Mounting holes can be formed in the mechanical block for securing optical elements. At least one semiconductor laser array die can be secured to the mechanical block at the integrated slots, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel.
1 . A 3D package for semiconductor thermal management as part of a printing system, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept a cooling liquid therethrough, a first tubular connection for providing the cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
at least one semiconductor laser array die, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel;
a lens array and mounting holes formed in the mechanical block for securing the lens array aligned with the at least one semiconductor laser array die to produce imaging with light from pixels of the at least one semiconductor laser array die onto a blanket cylinder associated with the printing system;
a vapor extraction unit mounted to a vapor extraction mount coupled to the 3D mechanical block and placed close to a focus area of the lens array, wherein the vapor extraction unit extracts fountain solution vapor generated by selective laser heating from a plurality of independently addressable surface emitting lasers;
wherein the at least one semiconductor laser array die further comprises the plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers operating at a power level reaching 50 mW and requiring thermal management; and
wherein each independently addressable semiconductor laser among the plurality of independently addressable surface emitting lasers further comprises at least one aperture operable in common with an associated address trace line to attain a larger effective aperture size, and wherein the at least one aperture further comprises a non-symmetric aperture shape configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers.
2 . The 3D package of claim 1 , wherein the address trace line associated with each of the plurality of independently addressable surface emitting lasers is fabricated to be at no more than a 22 micrometer pitch with respect to each other.
3 . The 3D package of claim 1 , wherein the address trace line is fabricated at a width that allows low sheet resistance and negligible voltage drops when electrified with a signal during operation of the semiconductor laser array.
4 . The 3D package of claim 1 , further comprising an electrical contact pad associated with the address trace line for each independently addressable semiconductor laser, wherein each electrical contact pad is configured to accept wire bonding.
5 . The 3D package of claim 1 , wherein the plurality of independently addressable surface emitting lasers are arranged along two rows with one set of address lines coming in from a top of the common substrate chip and are connecting to a first row of independently addressable surface emitting lasers and another set of address lines coming in from the bottom of the common substrate chip and are connecting to a second row of independently addressable surface emitting lasers.
6 . The 3D package of claim 5 , further comprising a driver circuit attached to each of a top row and a bottom row of a wire bonding to the electrical pads associated with each of the top row and bottom row.
7 . The 3D package claim 5 , wherein the first and second rows are offset with respect to each other to form an interdigitated linear array of light emitters on nor more than a 22 micrometer pitch.
8 . The 3D package of claim 5 , wherein the common substrate chip is fabricated at 21 mm long by 2 mm wide and contains at least 1000 independently addressable surface emitting lasers.
9 . The 3D package of claim 5 , further comprising more than one common substrate chip tiled and stitched together side-by-side to provide an at least 11-inch wide, 1200 pdi imager.
10 . The 3D package of claim 5 , further comprising more than one common substrate chip tiled and stitched together in a staggered arrangement to provide an at least 11-inch wide, 1200 pdi imager with timing delays associated with each of the more than one common substrate chip in the staggered arrangement.
11 . A 3D package for semiconductor thermal management, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept a cooling liquid therethrough, a first tubular connection for providing the cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
at least one semiconductor laser array die secured to the mechanical block, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel;
a lens array and mounting holes formed in the mechanical block for securing the lens array aligned with the at least one semiconductor laser array die to produce imaging with light from pixels of the at least one semiconductor laser array die onto a blanket cylinder associated with the printing system;
a vapor extraction unit mounted to a vapor extraction mount coupled to the 3D mechanical block and placed close to a focus area of the lens array, wherein the vapor extraction unit extracts fountain solution vapor generated by selective laser heating from a plurality of independently addressable surface emitting lasers;
wherein the at least one semiconductor laser array die further comprises the plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers; and
wherein each independently addressable semiconductor laser among the plurality of independently addressable surface emitting lasers further comprises at least one aperture operable in common with an associated address trace line to attain a larger effective aperture size, and wherein the at least one aperture further comprises a non-symmetric aperture shape configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers.
12 . The 3D package of claim 11 , wherein the address trace line associated with each of the plurality of independently addressable surface emitting lasers is fabricated to be at no more than a 22 micrometer pitch with respect to each other.
13 . A 3D package for semiconductor thermal management, comprising:
a 3D submount forming a mechanical block including at least one embedded channel formed within the mechanical block and configured to accept a cooling liquid therethrough, a first tubular connection for providing the cooling liquid to the at least one embedded channel, and a second tubular connection for removing cooling liquid from the at least one embedded channel;
at least one semiconductor laser array die secured to the mechanical block, wherein the at least one semiconductor laser array die is kept cool by the cooling liquid flowing through the at least one embedded channel;
a lens array and mounting holes formed in the mechanical block for securing the lens array aligned with the at least one semiconductor laser array die to produce imaging with light from pixels of the at least one semiconductor laser array die onto a blanket cylinder associated with the printing system;
a vapor extraction unit mounted to a vapor extraction mount coupled to the 3D mechanical block and placed close to a focus area of the lens array, wherein the vapor extraction unit extracts fountain solution vapor generated by selective laser heating from a plurality of independently addressable surface emitting lasers;
wherein the at least one semiconductor laser array die further comprises the plurality of independently addressable surface emitting lasers arranged in a linear array on a common substrate chip and including a common cathode and a dedicated channel associated with an address trace line for each laser of the plurality of independently addressable surface emitting lasers; and
wherein each independently addressable semiconductor laser among the plurality of independently addressable surface emitting lasers further comprises at least more than one aperture operable in common with an associated address trace line to attain a larger effective aperture size.
14 . The 3D package of claim 13 , wherein each of the more than one aperture of the plurality of surface emitting lasers further comprises a non-symmetric aperture shape configured to fit within a pitch of each address trace line associated with each channel for each of the plurality of independently addressable surface emitting lasers.