Granted Patent B2

US 12,645,375 · App. 18/334,399 · Granted Jun 2, 2026

Inventor: Koying Huang (San Jose, CA)

Assignee: Winbond Electronics Corp.

G06F3/0625G06F3/0659G06F3/0679

Abstract

Claims (71)

1 . An erase method for a non-volatile memory device comprising:

initiating an erase operation on a block of memory cells by applying an erase condition;

performing an erase verification procedure on at least a portion of the block of memory cells using an erase verify voltage;

performing a detection procedure on at least a portion of the block of memory cells using a post program verify voltage between a final erase verify voltage and a final post program verify voltage to detect whether leakage current above a threshold is present in the block of memory cells passed the erase verification procedure;

iteratively adjusting the erase verify voltage and the post program verify voltage, and repeating the steps of applying the erase condition, performing the erase verification procedure using the adjusted erase verify voltage, and performing the detection procedure using the adjusted post program verify voltage until the adjusted erase verify voltage has reached the final erase verify voltage and the adjusted post program verify voltage has reached the final post program verify voltage; and

finishing the erase operation when the adjusted erase verify voltage has reached the final erase verify voltage and the adjusted post program verify voltage has reached the final post program verify voltage.

2 . The erase method of claim 1 ,

wherein performing the erase verification procedure comprises:

determining whether a threshold voltage distribution of at least the portion of the block of memory cells is lower than the erase verify voltage or the adjusted erase verify voltage;

having determined that at least the portion of the block of memory cells has passed the erase verification procedure in response to the threshold voltage distribution of at least the portion of the block of memory cells being lower than the erase verify voltage or the adjusted erase verify voltage; and

having determined that at least the portion of the block of memory cells has failed the erase verification procedure in response to a portion of the threshold voltage distribution of at least the portion of the block of memory cells not being lower than the erase verify voltage or the adjusted erase verify voltage.

3 . The erase method of claim 2 , further comprising:

determining whether the adjusted erase verify voltage has reached the final erase verify voltage and whether the adjusted post program verify voltage has reached the final post program verify voltage when the leakage current above the threshold is not present,

wherein iteratively adjusting the erase verify voltage comprises:

adjusting the erase verify voltage when an erase pulse loop count is equal to 1, or in response to determining that the adjusted erase verify voltage has not reached the final erase verify voltage and the adjusted post program verify voltage has not reached the final post program verify voltage.

4 . The erase method of claim 2 , wherein repeating the step of applying the erase condition comprises:

applying the erase condition to the block of memory cells again in response to having determined that at least the portion of the block of memory cells has failed the erase verification procedure.

5 . The erase method of claim 3 further comprising:

incrementing the erase pulse loop count in response to having determined that at least the portion of the block of memory cells has failed the erase verification procedure,

wherein repeating the step of applying the erase condition comprises:

applying the same erase condition to the block of memory cells if the erase pulse loop count is not larger than an expected number; and

adjusting the erase condition and then applying the adjusted erase condition to the block of memory cells if the erase pulse loop count is larger than an expected number.

6 . The erase method of claim 5 , wherein adjusting the erase condition comprises:

adjusting the erase condition according to a first step level before-when the leakage current above the threshold is not present; and

adjusting the erase condition according to a second step level smaller than the first step level when the leakage current above the threshold is present.

7 . The erase method of claim 1 further comprising:

determining that the leakage current above the threshold is not present in response to a threshold voltage distribution of the block of memory cells being higher than the post program verify voltage,

determining that the leakage current above the threshold is present in response to a portion of the threshold voltage distribution of the block of memory cells being not higher than the post program verify voltage, and

changing the erase condition to be applied only to the portion of the block of memory cells rather than the entire block of memory cells in response to determining that the leakage current above the threshold is present.

8 . The erase method of claim 1 , further comprising:

performing a post program procedure to increase a threshold voltage distribution of the block of memory cells when the leakage current above the threshold is present.

9 . The erase method of claim 1 , wherein the erase verification procedure is performed for the portion of a block of memory cells rather than the entire block of memory cells.

10 . The erase method of claim 1 , further comprising:

adjusting the erase condition according to a first step level when the leakage current above the threshold is not present; and

adjusting the erase condition according to a second step level smaller than the first step level when the leakage current above the threshold is present.

11 . A memory device comprising:

a block of memory cells, and

a controller coupled to the block of memory cells and is configured to:

initiate an erase operation on a block of memory cells by applying an erase condition;

perform an erase verification procedure on at least a portion of the block of memory cells using an erase verify voltage;

perform a detection procedure on at least a portion of the block of memory cells using a post program verify voltage between a final erase verify voltage and a final post program verify voltage to detect whether leakage current above a threshold is present in the block of memory cells passed the erase verification procedure;

iteratively adjust the erase verify voltage and the post program verify voltage, and repeatedly apply the erase condition, perform the erase verification procedure using the adjusted erase verify voltage, and perform the detection procedure using the adjusted post program verify voltage, until the adjusted erase verify voltage has reached the final erase verify voltage and the adjusted post program verify voltage has reached the final post program verify voltage; and

finish the erase operation when the adjusted erase verify voltage has reached the final erase verify voltage and the adjusted post program verify voltage has reached the final post program verify voltage.

12 . The memory device of claim 11 ,

wherein the controller is configured to perform the erase verification procedure by:

determining whether a threshold voltage distribution of at least the portion of the block of memory cells is lower than the erase verify voltage or the adjusted erase verify voltage;

having determined that at least the portion of the block of memory cells has passed the erase verification procedure in response to the threshold voltage distribution of at least the portion of the block of memory cells being lower than the erase verify voltage or the adjusted erase verify voltage; and

having determined that at least the portion of the block of memory cells has failed the erase verification procedure in response to a portion of the threshold voltage distribution of at least the portion of the block of memory cells not being lower than the erase verify voltage or the adjusted erase verify voltage.

13 . The memory device of claim 12 , wherein the controller is further configured to determine whether the adjusted erase verify voltage has reached the final erase verify voltage and whether the adjusted post program verify voltage has reached the final post program verify voltage when the leakage current above the threshold is not present,

wherein the controller is configured to iteratively adjust the erase verify voltage by:

adjusting the erase verify voltage when an erase pulse loop count is equal to 1, or in response to determining that the adjusted erase verify voltage has not reached the final erase verify voltage and the adjusted post program verify voltage has not reached the final post program verify voltage.

14 . The memory device of claim 12 , wherein the controller is further configured to repeat the step of applying the erase condition by:

applying the erase condition to the block of memory cells again in response to having determined that at least the portion of the block of memory cells has failed the erase verification procedure.

15 . The memory device of claim 13 , wherein the controller is further configured to:

increment the erase pulse loop count in response to having determined that at least the portion of the block of memory cells has failed the erase verification procedure,

wherein the controller is configured to repeat the step of applying the erase condition by:

applying the same erase condition to the block of memory cells if the erase pulse loop count is not larger than an expected number-again, and

adjusting the erase condition and then applying the adjusted erase condition to the block of memory cells if the erase pulse loop count is larger than an expected number.

16 . The memory device of claim 15 , wherein the controller is configured to adjust the erase condition by:

adjusting the erase condition according to a first step level when the leakage current above the threshold is not present; and

adjusting the erase condition according to a second step level smaller than the first step level when the leakage current above the threshold is present.

17 . The memory device of claim 11 , wherein the controller is further configured to:

determine that the leakage current above the threshold is not present in response to a threshold voltage distribution of the block of memory cells being higher than the post program verify voltage,

determine that the leakage current above the threshold is present in response to a portion of the threshold voltage distribution of the block of memory cells being not higher than the post program verify voltage, and

change the erase condition to be applied only to the portion of the block of memory cells rather than the entire block of memory cells in response to determining that the leakage current above the threshold is present.

18 . The memory device of claim 11 , wherein the controller is further configured to:

perform a post program procedure to increase a threshold voltage distribution of the block of memory cells when the leakage current above the threshold is present.

19 . The memory device of claim 11 , wherein the erase verification procedure is performed for the portion of a block of memory cells rather than the entire block of memory cells.

20 . The memory device of claim 11 , wherein the controller is further configured to:

adjust the erase condition according to a first step level when the leakage current above the threshold is not present; and

adjust the erase condition according to a second step level smaller than the first step level when the leakage current above the threshold is present.

Assignments (1)

Continuity (1)

References Cited (43)