Variable dispatch walk
A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.
1 . A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:
in response to a first dispatch command, dispatch a first plurality of thread groups to a set of processing circuits having access to a cache in a first dispatch order based on shared data to be used by some thread groups but not all thread groups of the first plurality of thread groups, wherein the first dispatch order comprises dispatching a first thread group of the first plurality of thread groups immediately after a second thread group of the first plurality of thread groups based on an amount of data stored at the cache that is shared by the first thread group and the second thread group; and
in response to a second dispatch command, dispatch a second plurality of thread groups to the set of processing circuits in a second dispatch order, the second dispatch order different from the first dispatch order.
2 . The non-transitory computer readable medium of claim 1 , wherein the set of executable instructions are to manipulate at least one processor to:
store an access pattern that indicates the first dispatch order at a programmable table.
3 . The non-transitory computer readable medium of claim 2 , wherein the set of executable instructions are to manipulate at least one processor to:
store the access pattern at a programmable table in response to a pattern command.
4 . The non-transitory computer readable medium of claim 2 , wherein:
the second dispatch order is based on a second access pattern that is different from the access pattern.
5 . The non-transitory computer readable medium of claim 1 , wherein:
the first plurality of thread groups is organized according to at least two dimensions.
6 . The non-transitory computer readable medium of claim 1 , wherein the first dispatch order comprises one of:
a Hilbert curve, Morton curve pattern, or a z-order walking pattern.
7 . The non-transitory computer readable medium of claim 1 , wherein:
the set of processing circuits comprise a shader of a graphics processing unit.
8 . A method, comprising:
in response to receiving a first command, dispatching a first plurality of thread groups to a set of processing circuits having access to a cache in a first dispatch order based on shared data to be used by some thread groups but not all thread groups of the first plurality of thread groups, wherein the first dispatch order comprises dispatching a first thread group of the first plurality of thread groups immediately after a second thread group of the first plurality of thread groups based on an amount of data stored at the cache that is shared by the first thread group and the second thread group; and
in response to receiving a second command, dispatching a second plurality of thread groups in a second dispatch order to the set of processing circuits, the second dispatch order different from the first dispatch order.
9 . The method of claim 8 , wherein:
the first plurality of thread groups is organized according to at least two dimensions.
10 . The method of claim 8 , wherein:
an access pattern that indicates the first dispatch order is stored at a programmable table.
11 . The method of claim 8 , wherein:
the first dispatch order is determined based on data to be used by the first plurality of thread groups as part of one or more data swaps.
12 . The method of claim 8 , wherein the first dispatch order comprises one of:
a Hilbert curve, Morton curve pattern, or a z-order walking pattern.
13 . A processor comprising:
a set of processing circuits having access to a cache; and
a dispatch unit configured to:
in response to a first dispatch command, dispatch a first plurality of thread groups to a set of processing circuits in a first dispatch order based on shared data to be used by some thread groups but not all thread groups of the first plurality of thread groups, wherein the first dispatch order comprises dispatching a first thread group of the first plurality of thread groups immediately after a second thread group of the first plurality of thread groups based on an amount of data stored at the cache that is shared by the first thread group and the second thread group; and
in response to a second dispatch command, dispatch a second plurality of thread groups to the set of processing circuits in a second dispatch order, the second dispatch order different from the first dispatch order.
14 . The processor of claim 13 , further comprising:
a programmable table to store a plurality of access patterns including an access pattern that indicates the first dispatch order.
15 . The processor of claim 13 , wherein:
the first plurality of thread groups is organized according to at least three dimensions.
16 . The processor of claim 13 , wherein the first dispatch order comprises one of:
a Hilbert curve, Morton curve pattern, or a z-order walking pattern.
17 . The processor of claim 13 , wherein:
the processor comprises a graphics processing unit and the set of processing circuits comprise a shader.