Convolutional neural network operations
Methods and systems are disclosed for executing operations on single-instruction-multiple-data (SIMD) units. Techniques disclosed perform a dot product operation on input data during one computer cycle, including convolving the input data, generating intermediate data, and applying one or more transitional operations to the intermediate data to generate output data. Aspects described, wherein the input data is an input to a layer of a convolutional neural network and the generated output data is the output of the layer.
1 . A method for executing operations in parallel comprising:
loading, by a lane of a wave executing on an accelerated processing unit (APU), input data into vector general purpose registers (VGPRs) of the lane; and
in response to a single fused dot-product instruction, performing, by the lane, within a single clock cycle of the lane, a fused operation that generates output data, the fused operation comprising:
convolving a data element of the input data, using operands resident in the VGPRs of the lane, to generate an intermediate data element; and
in the same single clock cycle, applying one or more transitional operations including at least a rectifying operation to the intermediate data element, generating an output data element of the output data.
2 . The method of claim 1 , further comprising:
performing, by the lane, within the same single clock cycle of the lane, a dot product operation, comprising:
convolving a second data element of the input data, generating a second intermediate data element, and
applying the one or more transitional operations to the second intermediate data element, generating a second output data element of the output data.
3 . The method of claim 1 , wherein the one or more transitional operations further include one of a reformatting operation or a clamping operation.
4 . The method of claim 1 , wherein the input data is an input to a layer of a convolutional neural network and the output data is the output of the layer.
5 . The method of claim 1 , wherein:
the input data comprise pixels of an image, including a pixel and a pixel-block, centered at the pixel; and
the convolving comprises a dot product of the pixel-block and a kernel of weights, the pixel-block and the kernel are stored in the VGPRs of the lane.
6 . The method of claim 5 , wherein when a first portion of the pixel-block is stored in the VGPRs of the lane and a second portion of the pixel-block is stored in VGPRs of another lane in the wave, the lane accesses the second portion from the VGPRs of the other lane.
7 . The method of claim 5 , wherein when a first portion of the pixel-block is stored in the VGPRs of the lane and a second portion of the pixel-block is not stored in the VGPRs of the lane, the data from the second portion is replaced by data from the first portion.
8 . The method of claim 7 , wherein the generated output data is replaced with output data that was generated by a lane of a second wave.
9 . The method of claim 1 , wherein:
the input data are channel data of a pixel of an image, and
the convolving comprises a dot product of the channel data and a kernel of weights, the channel data and the kernel are stored in the VGPRs of the lane.
10 . A circuitry for executing operations in parallel, comprising:
at least one processor; and
memory storing instructions that, when executed by the at least one processor, cause the circuitry to:
load, by a lane of a wave executing on the at least one processor, input data into VGPRs of the lane; and
in response to a single fused dot-product instruction, perform, by the lane, a within a single clock cycle of the lane, a fused operation that generates output data, the fused operation comprising:
convolving a data element of the input data, using operands resident in the VGPRs of the lane, to generate an intermediate data element; and
in the same single clock cycle, applying one or more transitional operations including at least a rectifying operation to the intermediate data element, generating an output data element of the output data.
11 . The circuitry of claim 10 , further comprising instructions that cause the circuitry to:
perform, by the lane, within the same single clock cycle of the lane, a dot product operation, comprising:
convolving a second data element of the input data, generating a second intermediate data element, and
applying the one or more transitional operations to the second intermediate data element, generating a second output data element of the output data.
12 . The circuitry of claim 10 , wherein the one or more transitional operations further includes are one of a reformatting operation or a clamping operation.
13 . The circuitry of claim 10 , wherein the input data is an input to a layer of a convolutional neural network and the output data is the output of the layer.
14 . The circuitry of claim 10 , wherein:
the input data comprise pixels of an image, including a pixel and a pixel-block, centered at the pixel; and
the convolving comprises a dot product of the pixel-block and a kernel of weights, the pixel-block and the kernel are stored in the VGPRs of the lane.
15 . The circuitry of claim 14 , wherein when a first portion of the pixel-block is stored in the VGPRs of the lane and a second portion of the pixel-block is stored in VGPRs of another lane in the wave, the lane accesses the second portion from the VGPRs of the other lane.
16 . The circuitry of claim 14 , wherein when a first portion of the pixel-block is stored in the VGPRs of the lane and a second portion of the pixel-block is not stored in the VGPRs of the lane, the data from the second portion is replaced by data from the first portion.
17 . The circuitry of claim 16 , wherein the generated output data is replaced with output data that was generated by a lane of a second wave.
18 . The circuitry of claim 10 , wherein:
the input data are channel data of a pixel of an image, and
the convolving comprises a dot product of the channel data and a kernel of weights, the channel data and the kernel are stored in the VGPRs of the lane.
19 . A non-transitory computer-readable medium comprising instructions executable by at least one processor to perform a method for executing operations in parallel, the method comprising:
loading, by a lane of a wave executing on an accelerated processing unit (APU), input data into VGPRs of the lane; and
in response to a single fused dot-product instruction, performing, by the lane, within a single clock cycle of the lane, a fused operation that generates output data, the fused operation comprising:
convolving a data element of the input data, using operands resident in the VGPRs of the lane, to generate an intermediate data element; and
in the same single clock cycle, applying one or more transitional operations including at least a rectifying operation to the intermediate data element, generating an output data element of the output data.
20 . The medium of claim 19 , further comprising:
performing, by the lane, within the same single clock cycle of the lane, a dot product operation, comprising:
convolving a second data element of the input data, generating a second intermediate data element, and
applying the one or more transitional operations to the second intermediate data element, generating a second output data element of the output data.