Memory device generating voltage responsive to temperature and method of operating the same
A memory device includes a memory cell array including a plurality of memory cells, a temperature sensor configured to measure an internal temperature and generate a temperature compensation code corresponding to the internal temperature, a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code. The temperature sensor and the voltage control circuit are may be located at different positions relative to the memory cell array.
1 . A memory device comprising:
a memory cell array including a plurality of memory cells;
a temperature sensor configured to measure an internal temperature of at least one of: the memory cell array and the memory device, the temperature sensor being additionally configured to generate a temperature compensation code corresponding to the internal temperature;
a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code; and
a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array, responsive to the conversion temperature code,
wherein the temperature sensor and the voltage control circuit are located at different positions relative to the memory cell array location.
2 . The memory device of claim 1 , further comprising:
a voltage register configured to store a default voltage code indicating a default level of the voltage.
3 . The memory device of claim 2 , wherein the voltage control circuit comprises a temperature code converter configured to generate the conversion temperature code by performing a shift operation on the temperature compensation code.
4 . The memory device of claim 3 , wherein the voltage control circuit comprises a voltage code generator configured to generate a compensation voltage code to compensate for the level of the voltage responsive to the default voltage code and the conversion temperature code.
5 . The memory device of claim 4 , wherein the voltage generation circuit comprises a charge pump configured to perform a pump operation of generate the voltage.
6 . The memory device of claim 5 , wherein the voltage generation circuit comprises a voltage level compensator configured to change the level of the voltage output from the charge pump to a level of the compensation voltage according to the compensation voltage code.
7 . The memory device of claim 1 , wherein the temperature sensor is located under the memory cell array, and
the voltage control circuit is located on the memory cell array.
8 . The memory device of claim 1 , wherein the temperature sensor outputs the temperature compensation code corresponding to the internal temperature and a correction code select signal received from the voltage control circuit.
9 . The memory device of claim 1 , wherein the temperature sensor is located substantially at the geometric center of at least one of: the memory cell array and the memory device.
10 . The memory device of claim 1 , wherein the temperature sensor is located within a thermal isolation layer.
11 . The memory device of claim 10 , wherein the thermal isolation layer comprises at least one of: aluminum nitride, aluminum oxide, beryllium oxide, boron nitride and silicon carbide.
12 . A method of operating a memory device, the method comprising:
measuring an internal temperature by a temperature sensor positioned on a first surface of a memory cell array, and generating a temperature compensation code corresponding to the measured internal temperature;
generating a conversion temperature code converted from the temperature compensation code, by a voltage control circuit positioned on a second surface of the memory cell array;
outputting a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code; and
performing an operation on the memory cell array using the compensation voltage.
13 . The method of claim 12 , wherein generating the conversion temperature code comprises generating the conversion temperature code by performing a shift operation on the temperature compensation code.
14 . The method of claim 12 , wherein generating the conversion temperature code comprises generating a compensation voltage code responsive to a default voltage code indicating a default level of the voltage and the conversion temperature code.
15 . The method of claim 14 , wherein outputting the compensation voltage comprises changing the level of the voltage generated by a charge pump to a level of the compensation voltage according to the compensation voltage code.
16 . The method of claim 12 , wherein the first surface is a lower portion of the memory cell array, and
the second surface is an upper portion of the memory cell array.
17 . A memory device comprising:
a memory cell array including a plurality of memory cells;
a voltage register configured to store a default voltage code indicating a default level of a voltage used in an operation on the memory cell array;
a temperature sensor configured to measure an internal temperature and generate a temperature compensation code responsive to the internal temperature;
a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and output a compensation voltage code responsive to the default voltage code and the conversion temperature code; and
a voltage generation circuit configured to provide a compensation voltage obtained by compensate for a level of the voltage responsive to the compensation voltage code to the memory cell array,
wherein the memory cell array is positioned between the temperature sensor and the voltage control circuit.
18 . The memory device of claim 17 , wherein the voltage control circuit comprises a temperature code converter configured to generate the conversion temperature code by performing a shift operation on the temperature compensation code.
19 . The memory device of claim 17 , wherein the voltage generation circuit comprises:
a charge pump configured to generate the voltage; and
a voltage level compensator configured to change the level of the voltage to the level of the compensation voltage according to the compensation voltage code.
20 . The memory device of claim 17 , wherein the temperature sensor is located under the memory cell array, and
the voltage control circuit is located on the memory cell array.