High performance, non-volatile memory module
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.
1 . An integrated circuit (IC) chip comprising:
a buffer, the buffer comprising
a primary data interface to couple with a memory controller via a set of point-to-point link connections, the set of point-to-point link connections selectively enabled to provide a selectable width,
a secondary data interface to couple to at least two non-volatile memory devices disposed on a first memory module, and
bypass circuitry to selectively steer, from a first point-to-point link connection of the set of point-to-point link connections to a second point-to-point link connection of the set of point-to-point link connections, a read data transfer operation that is received from a second memory module at the first point-to-point link connection of the set of point-to-point link connections, and retransmitted to the memory controller via the second point-to-point link connection of the set of point-to-point link connections.
2 . The IC chip according to claim 1 , wherein the read data transfer operation is in accordance with a dynamic random access memory (DRAM) protocol.
3 . The IC chip according to claim 1 , wherein the set of point-to-point connections of the primary data interface comprise a first external pin and a second external pin, wherein the bypass circuitry is coupled to the first external pin and the second external pin, the bypass circuitry comprising a bypass path between the first external pin and the second external pin.
4 . The IC chip according to claim 1 , further comprising aggregation logic to aggregate and convert data between respective non-volatile and DRAM data formats.
5 . The IC chip according to claim 4 , wherein the aggregation logic includes:
a read data buffer to receive read block data and convert the read block data to column read data for a given read buffer operation; and
a write data buffer to receive column write data and convert the column write data to write block data for a given write buffer operation.
6 . The IC chip according to claim 5 , wherein the read data buffer and the write data buffer are configured such that column data accesses have a latency that matches a DRAM access latency.
7 . The IC chip according to claim 1 , further comprising:
a status signal generator to generate a status signal for transmission to the memory controller upon completion of operations associated with each of the respective read data buffer and write data buffer.
8 . The IC chip according to claim 1 , wherein:
the secondary data interface is to access the at least two non-volatile memory devices in parallel.
9 . The IC chip according to claim 1 , wherein:
the secondary data interface is to access the at least two non-volatile memory devices concurrently for independent accesses.
10 . The IC chip according to claim 1 , wherein:
the primary data interface is to transfer column read data to the memory controller as a pipelined transfer.
11 . The IC chip according to claim 1 , wherein:
the buffer includes at least two data interfaces coupled to the primary data interface.
12 . The IC chip according to claim 11 , wherein each of the at least two data interfaces includes:
a group of four data links defining a nibble; and
a timing link.
13 . The IC chip according to claim 12 , wherein the primary data interface is to couple to the memory controller and a DRAM module, and wherein:
first signals transferred between the memory controller and the primary data interface have a first phase alignment between a data link group and the timing link;
second signals transferred between the DRAM module and the primary data interface have a second phase alignment between the data link group and the timing link; and
wherein the first phase alignment is different than the second phase alignment.
14 . A method of operation in a buffer integrated circuit (IC) chip, the method comprising:
interfacing a memory controller with a primary data interface via a set of point-to-point link connections, the set of point-to-point link connections selectively enabled to provide a selectable width;
interfacing at least two non-volatile memory devices with a secondary data interface, the at least two non-volatile memory devices disposed on a first memory module; and
selectively steering, from a first point-to-point link connection of the set of point-to-point link connections to a second point-to-point link connection of the set of point-to-point link connections, a read data transfer operation that is received from a second memory module at the first point-to-point link connection of the set of point-to-point link connections, and retransmitted to the memory controller via the second point-to-point link connection of the set of point-to-point link connections.
15 . The method according to claim 14 , further comprising:
aggregating block read data for read operations and column write data for write operations; and
converting the block read data to column read data for read operations and the column write data to block write data for write operations.
16 . The method according to claim 15 , further comprising:
generating a status signal for transmission to the memory controller upon completion of operations associated with each of the respective read operations and write operations.
17 . The method according to claim 15 , wherein interfacing the at least two non-volatile memory devices with a secondary data interface comprises:
interfacing at least two non-volatile memory devices with the secondary data interface in parallel.
18 . The method according to claim 15 , wherein interfacing the at least two non-volatile memory devices with a secondary data interface comprises:
interfacing at least two non-volatile memory devices with the secondary data interface concurrently for independent accesses.
19 . The method according to claim 15 , wherein interfacing a memory controller with a primary data interface comprises:
transferring column read data to the memory controller as a pipelined transfer.
20 . An integrated circuit (IC) buffer chip, comprising:
a primary data interface to couple with a memory controller via a set of point-to-point link connections, the set of point-to-point link connections selectively enabled to provide a configurable width;
a secondary data interface to couple to at least two non-volatile memory devices disposed on a first memory module; and
bypass circuitry to selectively steer, from a first point-to-point link connection of the set of point-to-point link connections to a second point-to-point link connection of the set of point-to-point link connections, a dynamic random access memory (DRAM) read data transfer operation that is received from a second memory module at the first point-to-point link connection of the set of point-to-point link connections, and retransmitted to the memory controller via the second point-to-point link connection of the set of point-to-point link connections.