Memory and operation method thereof
An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.
1 . A memory comprising:
memory cell arrays, neighboring ones of which share a corresponding one of bit line sense amplifier arrays coupled to columns of the respective memory cell arrays;
a data transfer circuit configured to exchange data with an exterior;
switch arrays each configured to couple, when activated, the data transfer circuit to at least one of bit line sense amplifiers within a corresponding one of the bit line sense amplifier arrays; and
a control circuit configured to:
activate, during an active operation, first and second rows of respective first and second memory cell arrays that do not neighbor with each other among the memory cell arrays, and
access the activated first row by activating a first switch array while deactivating a second switch array, the first and second switch arrays respectively corresponding to the first and second memory cell arrays.
2 . The memory of claim 1 , wherein the activated second row is not accessed while accessing the activated first row.
3 . The memory of claim 1 , wherein the control circuit is configured to:
select the first row according to an active address input from the exterior during the active operation, and
select the second row according to a target row address when it is determined to perform a target row refresh operation during the active operation.
4 . The memory of claim 3 , wherein the control circuit is further configured to:
determine whether to perform the target row refresh operation during the active operation, by determining, whenever an active command is applied a predetermined number of times, whether the target row address is collected or not.
5 . The memory of claim 3 , further comprising:
a target row collection circuit configured to collect the target row address based on the active address or collect the target row address by random sampling.
6 . The memory of claim 1 , wherein the control circuit is configured to:
read, in response to a read command and a read address, data from memory cells selected by the read address in the activated first row.
7 . The memory of claim 1 , wherein the control circuit is configured to:
write, in response to a write command and a write address, write data to memory cells selected by the write address in the activated first row.
8 . The memory of claim 3 , wherein the control circuit is configured to:
precharge, after the active operation, the activated first row and the activated second row, in response to a precharge command.
9 . An operating method of a memory including memory cell arrays, neighboring ones of which share a corresponding one of bit line sense amplifier arrays coupled to columns of the respective memory cell arrays, and switch arrays each configured to couple, when activated, a data transfer circuit to at least one of bit line sense amplifiers within a corresponding one of the bit line sense amplifier arrays, the operating method comprising:
activating, during an active operation, first and second rows of respective first and second memory cell arrays that do not neighbor with each other among the memory cell arrays; and
accessing the activated first row by activating a first switch array while deactivating a second switch array, the first and second switch arrays respectively corresponding to the first and second memory cell arrays.
10 . The operating method of claim 9 , wherein the activated second row is not accessed while accessing the activated first row.
11 . The operating method of claim 9 , wherein the activating the first and second rows includes:
selecting the first row according to an active address input from an exterior during the active operation, and
selecting the second row according to a target row address when it is determined to perform a target row refresh operation during the active operation.
12 . The operating method of claim 11 , wherein the activating the first and second rows further includes:
determining whether to perform the target row refresh operation during the active operation, by determining, whenever an active command is applied a predetermined number of times, whether the target row address is collected or not.
13 . The operating method of claim 11 , further comprising:
collecting the target row address based on the active address or collecting the target row address by random sampling.
14 . The operating method of claim 9 , further comprising:
receiving a read command and a read address; and
reading, after accessing the activated first row, data from memory cells corresponding to the read address in the activated first row.
15 . The operating method of claim 9 , further comprising:
receiving a write command, a write address and a write data; and
writing, after accessing the activated first row, the write data from memory cells corresponding to the read address in the activated first row.
16 . The operating method of claim 9 , further comprising:
receiving a precharge command; and
precharging, after the activation operation, the first row and the second row, in response to the precharge command.