Register retention during device power collapse
Various aspects of the present disclosure generally relate to integrated circuits. In some aspects, a device may identify a register associated with the device. The device may identify, based at least in part on a formal based register retention analysis, that the register is to be retained during a power collapse associated with the device. The device may generate a register retention list that includes the register. The device may perform, after the power collapse, a hardware functional reset based at least in part on the register retention list. Numerous other aspects are described.
1 . A device, comprising:
one or more antennas; and
a processing system that includes one or more processors and one or more memories that store code and are coupled with the one or more processors, the processing system configured to cause the device to:
identify a register associated with the device;
identify, based at least in part on a formal based register retention analysis, that the register is to be retained during a power collapse associated with the device,
wherein the formal based register retention analysis is based at least in part on one or more of a register transfer level (RTL) design, initial design constraints, or a retention analysis property, and
wherein the initial design constraints are associated with a minimal set of design constraints, and additional design constraints are potentially added to identify additional registers that are not to be retained;
generate a register retention list that includes the register; and
perform, after the power collapse, a hardware functional reset based at least in part on the register retention list.
2 . The device of claim 1 , wherein the processing system, to identify whether the register is to be retained, is configured to cause the device to:
identify a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identify a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determine that the register is to not be retained based at least in part on the first value corresponding to the second value, wherein the register is excluded from the register retention list.
3 . The device of claim 2 , wherein the processing system is further configured to cause the device to:
identify a third value associated with the register, wherein the third value is associated with a value of the register upon a power collapse exit, wherein the register may be associated with mission mode activity without a software configuration sequence based at least in part on the second value corresponding to the third value.
4 . The device of claim 1 , wherein the processing system, to identify whether the register is to be retained, is configured to cause the device to:
identify a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identify a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determine that the register is to be retained based at least in part on the first value being different from the second value, wherein the register is included in the register retention list.
5 . The device of claim 1 , wherein the register is a non-control and non-status register (non-CSR).
6 . The device of claim 1 , wherein the register is included in the register retention list, and the register is not reset during the hardware functional reset based at least in part on the register being included in the register retention list.
7 . The device of claim 1 , wherein the register retention list is associated with a unified power format (UPF).
8 . The device of claim 1 , wherein the device is a system on a chip (SoC).
9 . A method, comprising:
identifying, by a device, a register associated with the device;
identifying, by the device and based at least in part on a formal based register retention analysis, that the register is to be retained during a power collapse associated with the device,
wherein the formal based register retention analysis is based at least in part on one or more of a register transfer level (RTL) design, initial design constraints, or a retention analysis property; and
wherein the initial design constraints are associated with a minimal set of design constraints, and additional design constraints are potentially added to identify additional registers that are not to be retained;
generating, by the device, a register retention list that includes the register; and
performing, by the device and after the power collapse, a hardware functional reset based at least in part on the register retention list.
10 . The method of claim 9 , wherein identifying whether the register is to be retained comprises:
identifying, by the device, a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identifying, by the device, a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determining, by the device, that the register is to be not retained based at least in part on the first value corresponding to the second value, wherein the register is excluded from the register retention list.
11 . The method of claim 10 , further comprising:
identifying, by the device, a third value associated with the register, wherein the third value is associated with a value of the register upon a power collapse exit, wherein the register may be associated with mission mode activity without a software configuration sequence based at least in part on the second value corresponding to the third value.
12 . The method of claim 9 , wherein identifying whether the register is to be retained comprises:
identifying, by the device, a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identifying, by the device, a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determining, by the device, that the register is to be retained based at least in part on the first value being different from the second value, wherein the register is included in the register retention list.
13 . The method of claim 9 , wherein the register is a non-control and non-status register (non-CSR).
14 . The method of claim 9 , wherein the register is included in the register retention list, and the register is not reset during the hardware functional reset based at least in part on the register being included in the register retention list.
15 . The method of claim 9 , wherein the register retention list is associated with a unified power format (UPF).
16 . The method of claim 9 , wherein the device is a system on a chip (SoC).
17 . A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:
one or more instructions that, when executed by one or more processors of a device, cause the device to:
identify a register associated with the device;
identify, based at least in part on a formal based register retention analysis, that the register is to be retained during a power collapse associated with the device,
wherein the formal based register retention analysis is based at least in part on one or more of a register transfer level (RTL) design, initial design constraints, or a retention analysis property; and
wherein the initial design constraints are associated with a minimal set of design constraints, and additional design constraints are potentially added to identify additional registers that are not to be retained;
generate a register retention list that includes the register; and
perform, after the power collapse, a hardware functional reset based at least in part on the register retention list.
18 . The non-transitory computer-readable medium of claim 17 , wherein the one or more instructions, to cause the device to identify whether the register is to be retained, cause the device to:
identify a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identify a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determine that the register is to not be retained based at least in part on the first value corresponding to the second value, wherein the register is excluded from the register retention list.
19 . The non-transitory computer-readable medium of claim 18 , wherein the one or more instructions further cause the device to:
identify a third value associated with the register, wherein the third value is associated with a value of the register upon a power collapse exit, wherein the register may be associated with mission mode activity without a software configuration sequence based at least in part on the second value corresponding to the third value.
20 . The non-transitory computer-readable medium of claim 17 , wherein the one or more instructions, to cause the device to identify whether the register is to be retained, cause the device to:
identify a first value associated with the register, wherein the first value is associated with an initial hardware reset value of the register;
identify a second value associated with the register, wherein the second value is associated with a value of the register immediately prior to the power collapse; and
determine that the register is to be retained based at least in part on the first value being different from the second value, wherein the register is included in the register retention list.