Hybrid timing windows in clock tree synthesis
A hybrid window scheme for defining timing windows during CTS. CTS is performed to generate an intermediate clock tree including a respective insertion delay for each of the one of more flip-flops. A set of clock timing constraints is generated for the plurality of slack values of each flip-flop such that every positive slack value of the plurality of slack values is prevented from becoming negative, a lowest negative slack value of the one or more negative slack values is prevented from becoming lower, and every negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than its current value. A second iteration of CTS is performed, constrained by the clock timing constraints, resulting in an enhanced clock tree.
1 . A system comprising:
one or more processors; and
a computer-readable storage medium storing instructions, which when executed by the one or more processors, cause the system to perform operations comprising:
accessing a circuit design comprising a clock network that comprises a flip-flop;
performing a first iteration of clock tree synthesis to generate an intermediate clock tree based on the clock network, the intermediate clock tree comprising an insertion delay for the flip-flop, such that the flip-flop is associated with a plurality of slack values based at least in part on the insertion delay of the flip-flop;
generating a set of clock timing constraints for the plurality of slack values of the flip-flop such that:
every positive slack value of the plurality of slack values is prevented from becoming negative; and
if the plurality of slack values comprises one or more negative slack values:
a lowest negative slack value of the one or more negative slack values is prevented from becoming lower; and
every individual negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than a current value of the individual negative slack value;
performing a second iteration of clock tree synthesis constrained by the set of clock timing constraints, the performing of the second iteration of clock tree synthesis resulting in an enhanced clock tree; and
generating a layout instance for the circuit design based on the enhanced clock tree.
2 . The system of claim 1 , wherein:
the set of clock timing constraints of the flip-flop allows a first negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value to become as low as the lowest negative slack value.
3 . The system of claim 1 , wherein:
the set of clock timing constraints of the flip-flop allows a first negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value to become as low as a balance point between the lowest negative slack value and a current value of the first negative slack value.
4 . The system of claim 3 , wherein:
the balance point is a mean of the lowest negative slack value and a current value of the first negative slack value.
5 . The system of claim 1 , wherein:
the plurality of slack values comprises:
an input setup slack value;
an output setup slack value;
an input hold slack value; and
an output hold slack value.
6 . The system of claim 5 , wherein:
the set of clock timing constraints for the flip-flop comprises a timing window.
7 . The system of claim 6 , wherein:
the timing window comprises a maximum increase and a maximum decrease for the insertion delay of the flip-flop.
8 . The system of claim 7 , wherein:
the maximum increase is equal to a lesser of the input setup slack value and the output setup slack value; and
the maximum decrease is equal to a lesser of the input hold slack value and the output hold slack value.
9 . The system of claim 1 , wherein the instructions further cause the system to, prior to performing the second iteration of clock tree synthesis:
relax the set of clock timing constraints, such that a first positive slack value of the flip-flop is allowed to become negative but prevented from becoming lower than a first negative value, the first negative value being determined based on a current value of the first positive slack value and a predetermined minimum window size.
10 . The system of claim 9 , wherein:
the first positive slack value is selected based on its proximity to zero.
11 . The system of claim 1 , wherein:
performing the second iteration of clock tree synthesis comprises adjusting the insertion delay of the flip-flop.
12 . The system of claim 1 , wherein:
performing the second iteration of clock tree synthesis comprises adjusting design parameters affecting the insertion delay of the flip-flop.
13 . The system of claim 12 , wherein:
the design parameters comprise one or more design parameters affecting power consumption.
14 . The system of claim 12 , wherein:
the design parameters comprise one or more design parameters affecting compliance with one or more design rules.
15 . The system of claim 1 , wherein:
generating the layout instance for the circuit design based on the enhanced clock tree comprises performing one or more additional iterations of generating constraints and performing clock tree synthesis.
16 . A method comprising:
accessing a circuit design comprising a clock network that comprises a flip-flop;
performing a first iteration of clock tree synthesis to generate an intermediate clock tree based on the clock network, the intermediate clock tree comprising a insertion delay for the flip-flop, such that the flip-flop is associated with a plurality of slack values based at least in part on the insertion delay of the flip-flop;
generating a set of clock timing constraints for the plurality of slack values of the flip-flop such that:
every positive slack value of the plurality of slack values is prevented from becoming negative; and
if the plurality of slack values comprises one or more negative slack values:
a lowest negative slack value of the one or more negative slack values is prevented from becoming lower; and
every individual negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than a current value of the individual negative slack value;
performing a second iteration of clock tree synthesis constrained by the set of clock timing constraints, the performing of the second iteration of clock tree synthesis resulting in an enhanced clock tree; and
generating a layout instance for the circuit design based on the enhanced clock tree.
17 . The method of claim 16 , wherein:
the set of clock timing constraints of the flip-flop allows a first negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value to become as low as the lowest negative slack value.
18 . The method of claim 16 , wherein:
the set of clock timing constraints of the flip-flop allows a first negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value to become as low as a balance point between the lowest negative slack value and a current value of the first negative slack value.
19 . The method of claim 16 , further comprising, prior to performing the second iteration of CTS:
relaxing the set of constraints for the flip-flop, such that a first positive slack value of the flip-flop is allowed to become negative but prevented from becoming lower than a first negative value, the first negative value being determined based on a current value of the first positive slack value and a predetermined minimum window size.
20 . A non-transitory computer-readable storage medium, the computer-readable storage medium comprising instructions that when executed by one or more processors of a system, cause the system to perform operations comprising:
accessing a circuit design comprising a clock network that comprises a flip-flop;
performing a first iteration of clock tree synthesis to generate an intermediate clock tree based on the clock network, the intermediate clock tree comprising an insertion delay for the flip-flop, such that the flip-flop is associated with a plurality of slack values based at least in part on the insertion delay of the flip-flop;
generating a set of clock timing constraints for the plurality of slack values of the flip-flop such that:
every positive slack value of the plurality of slack values is prevented from becoming negative; and
if the plurality of slack values comprises one or more negative slack values:
a lowest negative slack value of the one or more negative slack values is prevented from becoming lower; and
every individual negative slack value of the one or more negative slack values having a higher value than the lowest negative slack value is prevented from becoming lower than the lowest negative slack value but is allowed to become lower than a current value of the individual negative slack value;
performing a second iteration of clock tree synthesis constrained by the set of clock timing constraints, the performing of the second iteration of clock tree synthesis resulting in an enhanced clock tree; and
generating a layout instance for the circuit design based on the enhanced clock tree.