Micromachined thermistor
A micromachined apparatus includes micromachined thermistor having first and second ends physically and thermally coupled to a substrate via first and second anchor structures to enable a temperature-dependent resistance of the micromachined thermistor to vary according to a time-varying temperature of the substrate. The micromachined thermistor has a length, from the first end to the second end, greater than a linear distance between the first and second anchor structures.
1 . An integrated circuit device comprising:
a die having a substrate, a cover, an enclosed space defined in between the substrate and the cover, the enclosed space being hermitically sealed within the die relative to an environment external to the integrated circuit device, and a micromachined thermistor within the enclosed space, the micromachined thermistor being anchored to the substrate; and
wherein a body of the micromachined thermistor comprises a doped, crystalline semiconductor material.
2 . The integrated circuit device of claim 1 wherein the micromachined thermistor has an electrical path length within the enclosed space, wherein electrical couplings which connect the integrated circuit device to the micromachined thermistor are in proximity to one another relative to the path length, such that the path length within the enclosed space is substantially greater than a linear distance between the electrical couplings.
3 . The integrated circuit device of claim 2 wherein the path length is at least twice the linear distance between the electrical couplings.
4 . The integrated circuit device of claim 1 wherein the cover comprises a lid which has been bonded to the substrate.
5 . The integrated circuit device of claim 1 wherein the cover comprises a semiconductor layer which has been deposited over a release material, wherein the semiconductor layer is characterized by vents, through which the release material has been removed to at least partially free the micromachined thermistor from contact with the substrate and with the semiconductor layer, and wherein the integrated circuit device further comprises at least one plug, which closes the vents following removal of the release material.
6 . The integrated circuit device of claim 1 wherein the body further comprises a metal material.
7 . The integrated circuit device of claim 1 wherein the doped, crystalline semiconductor material comprises crystal silicon, doped with an N-type dopant.
8 . The integrated circuit device of claim 1 wherein the doped, crystalline semiconductor material comprises a first region, the first region having a first impurity dopant type, and a second region, the second region having a second impurity dopant type.
9 . The integrated circuit device of claim 1 further comprising a microelectromechanical systems (MEMS) resonator, the MEMS resonator also being hermitically sealed with a chamber relative to the environment external to the integrated circuit device.
10 . The integrated circuit device of claim 9 wherein the die is a first die, wherein the integrated circuit device comprises a second die, is in a stacked configuration relative the first die, and wherein the chamber that hermitically seals the MEMS resonator relative to the environment external to the integrated circuit device is in the second die.
11 . The integrated circuit device of claim 1 wherein the enclosed space comprises a vacuum.
12 . The integrated circuit device of claim 1 wherein the micromachined thermistor is encapsulated within the integrated circuit device.
13 . The integrated circuit device of claim 1 further comprising a microelectromechanical systems (MEMS) resonator also on the die.
14 . The integrated circuit device of claim 13 , further comprising clock generation circuitry, the clock generation circuitry operable to generate a timing signal dependent on an output of the MEMS resonator and dependent on an output of the thermistor.
15 . A method of fabricating an integrated circuit device, the method comprising:
forming a first die to have a substrate, a cover, an enclosed space defined in between the substrate and the cover, the enclosed space being hermitically sealed within the die relative to an environment external to the integrated circuit device, and a micromachined thermistor within the enclosed space, the micromachined thermistor in a manner such that it is anchored to the substrate; and
wherein forming the first die comprises forming a body of the micromachined thermistor so as to include a doped, crystalline semiconductor material.
16 . The method of claim 15 wherein the method further comprises forming the micromachined thermistor to have an electrical path length, within the enclosed space, and couplings which electrically connect the integrated circuit device to the micromachined thermistor, wherein the electrical couplings are in proximity to one another relative to the path length, such that the path length within the enclosed space is substantially greater than a linear distance between the electrical couplings.
17 . The method of claim 16 wherein the path length is at least twice the linear distance between the electrical couplings.
18 . The method of claim 15 wherein forming the first die comprises bonding a lid to the substrate, the cover comprising the lid.
19 . The method of claim 15 wherein:
the forming of the die comprises:
depositing a release material over the substrate,
depositing a semiconductor layer over a release material,
forming vents in the semiconductor layer,
etching the release material via the vents, to at least partially free the micromachined thermistor from contact with the substrate and with the semiconductor layer, and
plugging the vents, to close the vents following the etching of the release material; and
the cover comprises the semiconductor layer.
20 . The method of claim 15 wherein forming the body further comprises forming the body to include a metal material.
21 . The method of claim 15 wherein the doped, crystalline semiconductor material comprises crystal silicon, doped with an N-type dopant.
22 . The method of claim 15 wherein forming the die comprises forming the doped, crystalline semiconductor material to have a first region, with a first impurity dopant type, and a second region, with a second impurity dopant type.
23 . The method of claim 15 wherein the method further comprises forming a microelectromechanical systems (MEMS) resonator, in a manner such that the MEMS resonator is also hermitically sealed with a chamber relative to the environment external to the integrated circuit device.
24 . The method of claim 23 wherein the die is a first die, wherein the method further comprises fabricating the integrated circuit device so as to have a second die, in a stacked configuration relative the first die, and such that the chamber that hermitically seals the MEMS resonator relative to the environment external to the integrated circuit device is in the second die.