Memory, memory system and method of controlling storage device
A memory having a first authentication code includes a communication port configured to transmit information including debug data to or receive the information including debug data from the external device; and a debug port controller that is usable for blocking of a communication path connecting to the communication port. The debug port controller is configured to receive an authentication request including a second authentication code from an external device, determine whether the second authentication code matches the first authentication code, and block the communication path if the second authentication code is not determined to match the first authentication code. The communication port may be configured to be disabled until the second authentication code matches the first authentication code.
1 . A memory having a first authentication code, comprising:
a communication port configured to transmit information including debug data to or receive the information including the debug data from an external device;
an activation information memory configured to store activation information indicating whether the memory is activated for a first time; and
a debug port controller that is usable for blocking a communication path connecting to the communication port, wherein the debug port controller is configured to:
receive an authentication request including a second authentication code from the external device, wherein an authentication notification is sent to the external device when the memory is activated for the first time, and wherein sending the authentication notification causes at least the external device to send the authentication request;
determine whether the second authentication code matches the first authentication code; and
block the communication path if the second authentication code is not determined to match the first authentication code.
2 . The memory according to claim 1 , wherein the communication port is configured to be disabled until the second authentication code matches the first authentication code.
3 . The memory according to claim 1 , further comprising a communication permitter configured to permit the communication port.
4 . The memory according to claim 3 , wherein the communication port is configured to:
be disabled until the second authentication code matches the first authentication code; and
be permitted to start communications if the second authentication code is determined to match the first authentication code.
5 . The memory according to claim 4 , wherein the communication port is enabled to be used for debugging after being permitted to start communications by the communication permitter.
6 . The memory according to claim 4 , wherein the communication port is for a universal asynchronous receiver/transmitter (UART) or a system management (SM) bus, and wherein the memory further comprises a second communication port for JTAG.
7 . The memory according to claim 1 , further comprising:
a timer to measure time; and
a timer controller to stop the timer, wherein the timer controller is configured to cause the timer to measure the time until a predetermined time when it is confirmed that the memory is started for a second time or a later time based on the activation information.
8 . The memory according to claim 7 , further comprising a memory chip, and a controller configured to access the memory chip, wherein the timer measures the time independently of an operation of the controller.
9 . The memory according to claim 1 , further comprising a first chip, the first chip comprising a memory chip, and a controller configured to access the memory chip.
10 . The memory according to claim 1 , wherein the communication path is an electronic fuse.
11 . A memory system comprising:
a memory having a first authentication code; and
a host device having a second authentication code connected to the memory, wherein the host device is configured to transmit an authentication request including the second authentication code to the memory, the memory including:
a communication port configured to transmit information including debug data to or receive the information including the debug data from an external device;
an activation information memory configured to store activation information indicating whether the memory is activated for a first time; and
a debug port controller that is usable for blocking communication path connecting to the communication port, wherein the debug port controller is configured to:
receive the authentication request including the second authentication code from the external device, wherein an authentication notification is sent to the external device when the memory is activated for the first time indicated by the activation information, and wherein sending the authentication notification causes at least the external device to transmit the authentication request;
determine whether the second authentication code included in the authentication request matches the first authentication code; and
block the communication path if the second authentication code is not determined to match the first authentication code.
12 . The memory system according to claim 11 , wherein the host device is configured to transmit the authentication request including the second authentication code to the memory every time the memory is activated for the first time.
13 . A method of controlling a storage device including a communication port and having a first authentication code, the method including:
storing, in an activation information memory of the storage device, activation information indicating whether a memory is activated for a first time;
receiving an authentication request including a second authentication code from a host device, wherein an authentication notification is sent to the host device when the memory is activated for the first time indicated by the activation information, and wherein sending the authentication notification causes at least the host device to transmit the authentication request;
blocking the communication port so that debug data cannot be received if the first authentication code does not match the second authentication code; and
maintaining a communication port connection so that the debug data can be received if the first authentication code and the second authentication code match.
14 . The memory of claim 6 , wherein the second communication port is not allowed to be reconnected when the debug port controller determines the second authentication code does not match the first authentication code.
15 . The memory system of claim 11 , wherein the memory system further comprises a second communication port, and wherein the second communication port is not allowed to be reconnected when the debug port controller determines the second authentication code does not match the first authentication code.
16 . The method of claim 13 , wherein the storage device includes a debug port controller and a second communication port, and wherein the second communication port is not allowed to be reconnected when the debug port controller determines the second authentication code does not match the first authentication code.
17 . The memory of claim 1 , wherein the activation information correlates to an activation flag generated by software.