Storage device, memory controller, non-volatile memory device, and method of operating memory controller for controlling data output timing
A storage device includes non-volatile memory dies, and a memory controller that outputs a first data output command address packet and receives first data. The memory controller receives the first data from a first non-volatile memory die through a data bus, and sequentially outputs a second data output command packet that instructs a second non-volatile memory die among the plurality of non-volatile memory dies to output second data, a second select chip enable packet that selects the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die. The second select chip enable packet includes a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first delay information for delaying an output point in time of the second data.
1 . A storage device comprising:
a non-volatile memory device including a plurality of non-volatile memory dies; and
a memory controller configured to
output a first data output command address packet that instructs a first non-volatile memory die among the plurality of non-volatile memory dies to output first data, through a command address bus,
receive the first data from the first non-volatile memory die through a data bus, and
sequentially output a second data output command packet that instructs a second non-volatile memory die among the plurality of non-volatile memory dies to output second data, a second select chip enable packet that selects the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die, through the command address bus, and
wherein the second select chip enable packet comprises a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first delay information for delaying an output point in time of the second data.
2 . The storage device of claim 1 , wherein, after the first select chip terminate command packet is output, the memory controller receives the second data from the second non-volatile memory die and outputs a second select chip terminate command packet that terminates selection of the second non-volatile memory die.
3 . The storage device of claim 2 , wherein the memory controller outputs a third data output command packet for any one of the plurality of non-volatile memory dies different from the second non-volatile memory die, outputs a third select chip enable packet for the any one non-volatile memory die after outputting the third data output command packet, and outputs the second select chip terminate command packet after outputting the third select chip enable packet, and
wherein the third select chip enable packet comprises the first delay information.
4 . The storage device of claim 2 , wherein the memory controller outputs a third data output command packet for any one of the plurality of non-volatile memory dies different from the second non-volatile memory die after outputting the second select chip terminate command packet and outputs a third select chip enable packet for the any one non-volatile memory die after outputting the third data output command packet, and
wherein the third select chip enable packet comprises second delay information different from the first delay information.
5 . The storage device of claim 4 , wherein the second non-volatile memory die outputs the second data after a first delay time has passed from a point in time at which the second select chip enable packet is received, the first delay time being greater than a reference time, and
wherein the any one of the plurality of non-volatile memory dies outputs third data after the reference time has passed from a point in time at which the third select chip enable packet is received.
6 . The storage device of claim 1 , wherein, after outputting the second select chip enable packet, the memory controller outputs the first select chip terminate command packet when reception of the first data is completed.
7 . The storage device of claim 1 , wherein the memory controller transmits two-bit command address signals to the non-volatile memory device for every unit cycle, transmits twelve-bit command address signals transmitted for six unit cycles to the non-volatile memory device as one command address packet, and transmits a command address signal of at least one bit corresponding to the first delay information to the non-volatile memory device in at least one of fifth and sixth unit cycles of six cycles.
8 . The storage device of claim 1 , wherein the memory controller comprises:
a first command queue configured to store a first command packet for the first non-volatile memory die;
a second command queue configured to store a second command packet for the second non-volatile memory die; and
a command generator configured to generate the first select chip terminate command packet, the second data output command packet, and the second select chip enable packet, to enqueue the first select chip terminate command packet in the first command queue, and to enqueue the second data output command packet and the second select chip enable packet in the second command queue.
9 . The storage device of claim 1 , wherein the memory controller outputs a set feature command packet through the command address bus and, after outputting the set feature command packet, outputs at least one set feature data indicating a delay time for delaying an output point in time of data output from each of the plurality of non-volatile memory dies.
10 . A method of operating a memory controller, the method comprising:
receiving first data from a first non-volatile memory die;
inserting delay information in a second select chip enable packet that selects a second non-volatile memory die, the delay information delaying an output timing of second data and being based on whether a second data output command packet that instructs the second non-volatile memory die to output second data is output before a first select chip terminate command packet that terminates selection of the first non-volatile memory die is output; and
outputting a command packet including the second data output command packet, the second select chip enable packet, and the first select chip terminate command packet based on the delay information that is set.
11 . The method of claim 10 , wherein inserting the delay information comprises inserting first delay information including a first delay time that is greater than a default time in the second select chip enable packet based on the second data output command packet being output before the first select chip terminate command packet is output, and
wherein outputting the command packet comprises:
outputting the second data output command packet;
after the second data output command packet is output, outputting the second select chip enable packet in parallel with the first data; and
after the second select chip enable packet is output, outputting the first select chip terminate command packet.
12 . The method of claim 10 , wherein inserting the delay information comprises:
inserting second delay information including a default time in the second select chip enable packet based on the second data output command packet being output after the first select chip terminate command packet is output, and
wherein outputting the command packet comprises:
outputting the first select chip terminate command packet at a point in time at which reception of the first data is completed;
outputting the second data output command packet; and
after the second data output command packet is output, outputting the second select chip enable packet.
13 . The method of claim 10 , further comprising:
after outputting the command packet, receiving the second data from the second non-volatile memory die; and
outputting a second select chip terminate command packet at a point in time at which reception of the second data from the second non-volatile memory die is completed, the second select chip terminate command packet terminating selection of the second non-volatile memory die.
14 . The method of claim 13 , further comprising:
before the second select chip terminate command packet is output, outputting a third data output command packet that instructs any one of a plurality of non-volatile memory dies different from the second non-volatile memory die to output data;
after outputting the third data output command packet, outputting a third select chip enable packet that selects the any one of the plurality of non-volatile memory dies, and
after outputting the third select chip enable packet, outputting the second select chip terminate command packet,
wherein the third select chip enable packet comprises first delay information indicating a first delay time greater than a default time.
15 . The method of claim 13 , further comprising:
after outputting the second select chip terminate command packet, outputting a third data output command packet that instructs any one of a plurality of non-volatile memory dies different from the second non-volatile memory die to output data; and
after outputting the third data output command packet, outputting a third select chip enable packet that selects the any one of the plurality of non-volatile memory dies,
wherein the third select chip enable packet comprises second delay information indicating a default time.
16 . A non-volatile memory device comprising:
a memory cell array including a plurality of memory cells;
a control logic circuit configured to generate a buffer control signal based on a data output command received through a command address bus, to determine a data enable signal output timing of a data enable signal based on a select chip enable that is received through the command address bus and that includes delay information for delaying a data output timing of data, and to generate the data enable signal based on the data enable signal output timing;
a page buffer group configured to latch internal data stored in the memory cell array based on the buffer control signal; and
a data input/output circuit connected to a data bus based on the data enable signal and configured to output the latched internal data through the data bus.
17 . The non-volatile memory device of claim 16 , wherein the control logic circuit comprises:
a delay information reader configured to read the delay information and to generate a read result;
a register configured to store first timing data indicating a default time and second timing data indicating a delay time that is greater than the default time, and to output any one of the first timing data and the second timing data selected according to the read result;
a timer configured to count rising and falling edges of a clock signal up to a time corresponding to the any one of the first timing data and the second timing data provided by the register and to generate an enable signal when counting of the time is completed; and
a signal generator configured to generate the data enable signal based on the enable signal.
18 . The non-volatile memory device of claim 17 , wherein the delay information comprises a single bit that indicates a data output timing as the default time or that indicates that the data output timing is to be delayed more than the default time.
19 . The non-volatile memory device of claim 17 , wherein the control logic circuit further comprises a timing setter configured to set a value of the register based on a set feature command received through the command address bus and to set the second timing data of the register based on set feature data received through the command address bus.
20 . The non-volatile memory device of claim 16 , wherein, after receiving the select chip enable, the control logic circuit outputs a data disable signal based on a select chip terminate received through the command address bus, and
wherein the data input/output circuit releases a connection with the data bus based on the data disable signal.