High-reliability processing-in-memory with transpose support using split-6T SRAM
A processor has a Static Random Access Memory (SRAM) array with individual SRAM cells, each individual SRAM cell has six transistors including a first access transistor, a second access transistor, a first N-Channel Metal-Oxide Semiconductor (NMOS) transistor cross-coupled with a first P-Channel Metal-Oxide Semiconductor (PMOS) transistor forms a first inverter, and a second NMOS transistor cross-coupled with a second PMOS transistor forms a second inverter. Split word line drivers are connected to the SRAM array. The split word line drivers include left word line drivers and right word line drivers that are alternately activated to drive a single sense amplifier per bit line.
1 . A processor, comprising:
a Static Random Access Memory (SRAM) array with individual SRAM cells, each individual SRAM cell comprising six transistors including a first access transistor, a second access transistor, a first N-Channel Metal-Oxide Semiconductor (NMOS) transistor cross-coupled with a first P-Channel Metal-Oxide Semiconductor (PMOS) transistor to form a first inverter, a second NMOS transistor cross-coupled with a second PMOS transistor to form a second inverter;
split word line drivers connected to the SRAM array, the split word line drivers including left word line drivers and right word line drivers that are alternately activated to drive a single sense amplifier per bit line; and
a transpose write driver circuit connected to the SRAM array to implement a data transposition in the SRAM array and select a column of the SRAM array by driving both bit lines associated with the selected column to 0V; and
wherein the split word line drivers simultaneously write data to the selected column of the SRAM array.
2 . The processor of claim 1 wherein the split word line drivers read two rows simultaneously to simultaneously drive two outputs to two separate sense amplifiers connected to two separate bit lines.
3 . The processor of claim 1 wherein the data transposition is a bit-parallel to bit-serial transposition.
4 . The processor of claim 1 further comprising SRAM array column logic including a full-adder circuit, a carry latch circuit, and a mask register.
5 . The processor of claim 4 wherein the SRAM array column logic implements high-parallelism bit-serial arithmetic.
6 . The processor of claim 4 wherein the SRAM array column logic implements bit-serial addition in each column.
7 . The processor of claim 4 wherein the mask register stores a mask specifying whether data is written to bit cells by controlling enable signals to write buffers.