IP Library Granted Patent US 12,658,591
Granted Patent B2
US 12,658,591 · App. 18/341,768 · Granted Jun 16, 2026

Electronic apparatus

Inventor: Kazuyuki Hashimoto (Miaoli County, TW)
Assignee: Innolux Corporation
H01Q13/103H01Q3/242H01Q23/00
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Quick Facts
Patent No.
US 12,658,591
App. No.
18/341,768
Granted
Jun 16, 2026
Kind
B2
Abstract

An electronic apparatus is provided. The electronic apparatus includes a plurality of sets of cascaded units. Each one of the plurality of sets of cascaded units is electrically connected to a common data line and a common clock signal line. Each one of the plurality of sets of cascaded units forms a cascaded circuit.

Claims (35)

1 . An electronic apparatus, comprising:

a plurality of sets of cascaded units,

wherein each one of the plurality of sets of cascaded units is electrically connected to a common data line and a common clock signal line which provides a clock signal, and each one of the plurality of sets of cascaded units forms a cascaded circuit,

wherein each one of the cascaded units comprises:

a driving circuit, comprises at least one scan driver and at least one bias circuit; and

at least one tunable device, electrically connected to the driving circuit, and driven by the driving circuit,

wherein the at least one scan driver is directly connected to a timing controller through the common clock signal line which provides the clock signal,

wherein the at least one bias circuit of each one of the cascaded units is electrically connected to the common data line.

2 . The electronic apparatus according to claim 1 , wherein at least one scan driver is configured to output a scan signal to at least one bias circuit.

3 . The electronic apparatus according to claim 2 , wherein at least one scan driver is configured to receive a cascade input signal, and output a cascade output signal.

4 . The electronic apparatus according to claim 3 , wherein at least one scan driver comprises:

a flip-flop circuit, wherein a data input terminal of the flip-flop circuit is configured to receive the cascade input signal, and a clock control terminal of the flip-flop circuit is configured to receive a clock signal;

an inverter circuit, wherein an input terminal of the inverter circuit is configured to receive the clock signal; and

an AND gate, wherein a first input terminal of the AND gate is electrically connected to a data output terminal of the flip-flop circuit, a second terminal of the AND gate is electrically connected to an output terminal of the inverter circuit, and an output terminal of the AND gate is configured to output the scan signal.

5 . The electronic apparatus according to claim 2 , wherein at least one bias circuit comprises:

a transistor, configured to receive the scan signal; and

a capacitor, electrically connected to the transistor and the common data line through the transistor, and configured to store a data voltage,

wherein at least one bias circuit is configured to output a control signal to at least one tunable, corresponding to the data voltage.

6 . The electronic apparatus according to claim 5 , wherein the transistor and the capacitor constitute a constant voltage source circuit.

7 . The electronic apparatus according to claim 6 , wherein the constant voltage source circuit comprises a source follower amplifier.

8 . The electronic apparatus according to claim 6 , wherein the constant voltage source circuit comprises an operational amplifier.

9 . The electronic apparatus according to claim 1 , wherein the driving circuit is configured to drive at least two tunable devices.

10 . The electronic apparatus according to claim 9 , wherein the driving circuit comprises at least two scan drivers and at least two bias circuits.

11 . The electronic apparatus according to claim 10 , wherein at least two scan drivers form a shift register circuit.

12 . The electronic apparatus according to claim 1 , wherein the driving circuit is a discrete integrated circuit.

13 . The electronic apparatus according to claim 1 , wherein the driving circuit is a thin film transistor circuit.

14 . The electronic apparatus according to claim 1 , wherein the cascaded units of each one of the plurality of sets of cascaded units is arranged in a line.

15 . The electronic apparatus according to claim 1 , wherein the plurality of sets of cascaded units are arranged in a plurality of radial lines.

16 . The electronic apparatus according to claim 1 , further comprising:

a data driver, disposed in a first area of a substrate,

wherein the plurality of sets of cascaded units are disposed in a second area of the substrate, and the first area surrounds the second area.

17 . The electronic apparatus according to claim 1 , further comprising:

a data driver, disposed in a first area of a substrate,

wherein the plurality of sets of cascaded units are disposed in a second area of the substrate, and the second area surrounds the first area.

18 . The electronic apparatus according to claim 1 , wherein the plurality of sets of cascaded units are arranged in a plurality of orthogonal lines.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2023
From: HASHIMOTO, KAZUYUKI
To: INNOLUX CORPORATION
Reel/Frame 064193/0198 →
Continuity (2)
Provisional Application 63427846 · Nov 24, 2022
Related Publication 20240178571A1 · May 30, 2024
References Cited (3)
US 11468817B1 · Kim · 2022 [cited by examiner]
US 20010017566A1 · Nakahara · 2001 [cited by examiner]
US 20100034339A1 · Iwai · 2010 [cited by examiner]