Semiconductor devices including bonded semiconductor layers and manufacturing methods of the same
A semiconductor device includes: a semiconductor layer including a wire and an electrical element; and a plurality of metal pads on a surface of the semiconductor layer, wherein the plurality of metal pads includes a first metal pad and a second metal pad, wherein the second metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the first metal pad, and wherein the second metal pad is between a first region of the surface of the semiconductor layer where the first metal pad is and a second region of the surface of the semiconductor layer where a surface metal density is zero (0).
1 . A semiconductor device comprising:
a semiconductor layer, including a wire and an electrical element; and
a plurality of metal pads on a surface of the semiconductor layer,
wherein the plurality of metal pads includes a first metal pad and a second metal pad,
wherein the second metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the first metal pad,
wherein the second metal pad is between a first region of the surface of the semiconductor layer where the first metal pad is and a second region of the surface of the semiconductor layer where a surface metal density is zero (0),
wherein the first metal pad includes a real pad and a dummy pad,
wherein the real pad is electrically connected to the wire or the electrical element, and
wherein the dummy pad is not electrically connected to the wire or the electrical element.
2 . The semiconductor device of claim 1 , wherein the second metal pad is adjacent to an edge of the semiconductor layer.
3 . The semiconductor device of claim 1 , further comprising an align key adjacent to the first metal pad on the surface of the semiconductor layer.
4 . The semiconductor device of claim 1 , wherein the dummy pad is between the real pad and the second metal pad.
5 . The semiconductor device of claim 4 , wherein the second metal pad is between the dummy pad and the second region of the surface of the semiconductor layer.
6 . The semiconductor device of claim 1 , further comprising a third metal pad between the second metal pad and the second region of the surface of the semiconductor layer.
7 . The semiconductor device of claim 6 , wherein the third metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the second metal pad.
8 . The semiconductor device of claim 1 , wherein a topological change rate of the surface of the semiconductor layer is less than or equal to a permissible topology change rate expressed as:
Permissible Topology Change Rate[%/μm]=(Topology Change Reference[Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth[Å/%]).
9 . The semiconductor device of claim 1 , wherein a topological change rate of the surface of the semiconductor layer is less than or equal to a permissible topology change rate expressed as:
Permissible Topology Change Rate[%/pitch]={(Topology Change Reference[Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth[Å/%])}*Metal Pad Pitch[μm].
10 . The semiconductor device of claim 9 , wherein the topological change rate of the surface of the semiconductor layer is 3.6% per four metal pad pitches or less.
11 . The semiconductor device of claim 1 , wherein a diameter of the second metal pad on the surface of the semiconductor layer is 59.625% to 80.25% of a diameter of the first metal pad on the surface of the semiconductor layer.
12 . The semiconductor device of claim 1 , wherein a diameter of the first metal pad on the surface of the semiconductor layer is 8 micrometers (μm), and a diameter of the second metal pad on the surface of the semiconductor layer is 4.77 μm to 6.42 μm.
13 . A manufacturing method of a semiconductor device, the method comprising:
preparing a first semiconductor layer including a wire and an electrical element, wherein a plurality of metal pads is on a surface of the first semiconductor layer; and
stacking and bonding a second semiconductor layer on the surface of the first semiconductor layer,
wherein the plurality of metal pads includes a first metal pad and a second metal pad,
wherein the second metal pad is smaller in surface area or diameter on the surface of the first semiconductor layer than the first metal pad,
wherein the second metal pad is between a first region of the surface of the first semiconductor layer where the first metal pad is and a second region of the surface of the first semiconductor layer where a surface metal density is zero (0), and
wherein a topological change rate of the surface of the first semiconductor layer is less than or equal to a permissible topology change rate expressed as:
Permissible Topology Change Rate [%/μm]=(Topology Change Reference [Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth [Å/%]); or
Permissible Topology Change Rate [%/pitch]={(Topology Change Reference [Å/μm])/(Relation between Metal Pad Density and Bonded Surface Erosion Depth [Å/%])}*Metal Pad Pitch [μm].
14 . The manufacturing method of claim 13 , wherein the bonding is a hybrid bonding, and
wherein the hybrid bonding directly connects the first semiconductor layer and the second semiconductor layer.
15 . The manufacturing method of claim 13 , wherein the second metal pad is adjacent to an edge of the first semiconductor layer.
16 . The manufacturing method of claim 13 , wherein at least one of the first metal pad or the second metal pad includes a real pad and/or a dummy pad,
wherein the real pad is electrically connected to the wire or the electrical element, and
wherein the dummy pad is not electrically connected to the wire or the electrical element.
17 . The manufacturing method of claim 13 , wherein a diameter of the second metal pad on the surface of the first semiconductor layer is 59.625% to 80.25% of a diameter of the first metal pad on the surface of the first semiconductor layer.
18 . A semiconductor device comprising:
a silicon interposer;
a memory that includes a plurality of semiconductor chip dies stacked on the silicon interposer; and
a logic circuit on the silicon interposer, wherein the logic circuit includes a central processing unit or a graphics processing unit,
wherein at least one of the silicon interposer, the plurality of semiconductor chip dies, or the logic circuit includes a plurality of metal pads on a surface thereof,
wherein the plurality of metal pads includes a first metal pad and a second metal pad,
wherein the second metal pad is smaller in surface area or diameter on the surface than the first metal pad,
wherein the second metal pad is between a first region of the surface where the first metal pad is and a second region of the surface where a surface metal density is zero (0), and
wherein the semiconductor device further comprises an align key adjacent to the first metal pad on the surface of the at least one of the silicon interposer, the plurality of semiconductor chip dies, or the logic circuit.
19 . The semiconductor device of claim 18 , wherein the semiconductor device is a 2.5D semiconductor package or a 3D semiconductor package.
20 . The manufacturing method of claim 13 , wherein an align key is adjacent to the first metal pad on the surface of the first semiconductor layer.