Granted Patent B2

US 12,687,880 · App. 18/414,647 · Granted Jul 21, 2026

Inventors: Bicky A. Marquez (Kingston, CA); Ahmed Khaled (Kingston, CA); Joshua S. J. Baxter (Ottawa, CA); Alireza Samani (Ottawa, CA); Orad Reshef (Ottawa, CA); Bhavin J. Shastri (Kingston, CA); Douglas H. Wightman (Kingston, CA)

Assignee: Milkshake Technology Inc.

G06E1/04H04L9/0643H04L9/0819

Abstract

Claims (68)

1 . A photonic processor, comprising:

one or more photonic input circuits having one or more inputs to receive one or more photonic input signals, the one or more photonic input circuits configured to generate one or more photonic output values based on the one or more photonic input signals;

a first set of one or more photonic adders coupled to the one or more photonic input circuits, at least one first photonic adder of the first set of one or more photonic adders including a first feedback path configured to feed a first feedback signal from a first carry output of the at least one first photonic adder to a first input of the at least one first photonic adder, the at least one first photonic adder configured to generate a photonic sum of one or more photonic sums based at least in part on a portion of the one or more photonic output values and the first feedback signal; and

a second set of one or more photonic adders coupled to the first set of one or more photonic adders, at least one second photonic adder of the second set of one or more photonic adders including a second feedback path configured to feed a second feedback signal from a second carry output of the at least one second photonic adder to a second input of the at least one second photonic adder, the at least one second photonic adder configured to generate an updated version of a photonic input signal of the one or more photonic input signals based at least in part on a portion of the one or more photonic sums and the second feedback signal.

2 . The photonic processor of claim 1 , further comprising a feedback interface coupling one or more output of the at least one second photonic adder with the one or more inputs of the one or more photonic input circuits, the feedback interface configured to feed the updated version of the photonic input signal back to the one or more photonic input circuits.

3 . The photonic processor of claim 1 , wherein:

the one or more photonic input circuits are further configured to receive the one or more photonic input signals including one or more keys and one or more input messages; and

the at least one second photonic adder is further configured to:

generate the updated version of the photonic input signal that includes an updated value of a key of the one or more keys, and

generate, after a defined number of iterations of the photonic processor and based on the updated value of the key, a portion of a hash value.

4 . The photonic processor of claim 3 , wherein the one or more photonic input circuits include a photonic adder, the photonic adder comprising:

a first input configured to receive a key of the one or more keys;

a second input configured to receive the one or more input messages; and

a third feedback path configured to feed a third feedback signal from a third carry output of the photonic adder to a third input of the photonic adder, wherein

the photonic adder is configured to generate a photonic output value of the one or more photonic output values, based on the key, the one or more input messages and the third feedback signal.

5 . The photonic processor of claim 3 , wherein the first set of one or more photonic adders includes a photonic adder, the photonic adder comprising:

a first input configured to receive a first photonic sum value output from another photonic adder of the one or more photonic input circuits;

a second input configured to receive a key of the one or more keys; and

a third feedback path configured to feed a third feedback signal from a third carry output of the photonic adder to a third input of the photonic adder, wherein

the photonic adder is configured to generate a second photonic sum value, based on the first photonic sum value, the key and the third feedback signal.

6 . The photonic processor of claim 3 , wherein a photonic adder of the first set of one or more photonic adders comprises a first input that directly receives a key of the one or more keys, and a photonic adder of the second set of one or more photonic adders comprises a second input that directly receives another key of the one or more keys.

7 . The photonic processor of claim 1 , further comprising a photonic adder that includes:

at least a pair of inputs configured to receive a pair of photonic sum values output from a pair of photonic adders of the first set of one or more photonic adders;

a third feedback path configured to feed a third feedback signal from a third carry output of the photonic adder to another input of the photonic adder; and

one or more outputs configured to:

output a photonic sum value generated based on the pair of photonic sum values and the third feedback signal, and

provide the photonic sum value to the second set of one or more photonic adders.

8 . The photonic processor of claim 7 , further comprising a beam splitter coupled to the photonic adder and the second set of one or more photonic adders, the beam splitter configured to:

receive the photonic sum value;

split the received photonic sum value into a first photonic sum value and a second photonic sum value;

provide the first photonic sum value to a first photonic adder of the second set of one or more photonic adders; and

provide the second photonic sum value to a second photonic adder of the second set of one or more photonic adders.

9 . The photonic processor of claim 1 , wherein each of the at least one first photonic adder and the at least one second photonic adder comprises one or more nonlinear amplitude thresholders.

10 . The photonic processor of claim 1 , wherein the one or more photonic input circuits comprise one or more nonlinear XOR photonic gates that include one or more nonlinear amplitude thresholders.

11 . The photonic processor of claim 1 , wherein each of the at least one first photonic adder and the at least one second photonic adder includes one or more nonlinear XOR photonic gates, the one or more nonlinear XOR photonic gates comprises a cascaded connection of at least one of: one or more photonic combiners, one or more beam splitters, one or more nonlinear amplitude thresholders, and one or more phase shifters.

12 . The photonic processor of claim 1 , wherein the one or more photonic input circuits comprise at least one of: one or more photonic splitters, one or more photonic crossing gates, one or more photonic rotator circuits, one or more nonlinear XOR photonic gates, one or more photonic majority logic gates, and one or more photonic choose logic gates.

13 . The photonic processor of claim 1 , wherein the one or more photonic input circuits comprise one or more photonic rotator circuits, each of the one or more photonic rotator circuits configured to receive a time series photonic input and generate a time series photonic output as a time-shifted version of the time series photonic input.

14 . A non-transitory computer-readable storage medium comprising stored instructions that, when executed by at least one processor, cause the at least one processor to:

instruct one or more photonic input circuits of a photonic processor to generate one or more photonic output values based on one or more photonic input signals;

instruct at least one first photonic adder of a first set of one or more photonic adders of the photonic processor to:

receive a first feedback signal from a first carry output of the at least one first photonic adder, and

generate a photonic sum of one or more photonic sums, based at least in part on a portion of the one or more photonic output values and the first feedback signal; and

instruct at least one second photonic adder of a second set of one or more photonic adders of the photonic processor to:

receive a second feedback signal from a second carry output of the at least one second photonic adder, and

generate an updated version of a photonic input signal of the one or more photonic input signals, based at least in part on a portion of the one or more photonic sums and the second feedback signal.

15 . The computer-readable storage medium of claim 14 , wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to:

instruct the one or more photonic input circuits to receive the one or more photonic input signals including one or more keys and one or more input messages; and

instruct the at least one second photonic adder to generate the updated version of the photonic input signal that includes an updated value of a key of the one or more keys.

16 . The computer-readable storage medium of claim 15 , wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to instruct the at least one second photonic adder to:

feed the updated value of the key back to a photonic input circuit of the one or more photonic input circuits; and

generate, after a defined number of iterations of the photonic processor and based on the updated value of the key, a portion of a hash value.

17 . The computer-readable storage medium of claim 15 , wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to instruct a photonic adder of the one or more photonic input circuits to:

receive a key of the one or more keys;

receive the one or more input messages;

receive a third feedback signal from a third carry output of the photonic adder; and

generate a photonic output value of the one or more photonic output values, based on the key, the one or more input messages and the third feedback signal.

18 . The computer-readable storage medium of claim 14 , wherein the stored instructions comprise further stored instructions that, when executed, cause the at least one processor to instruct a photonic adder of the photonic processor to:

receive at least a pair of photonic sum values output from a pair of photonic adders of the first set of one or more photonic adders;

receive a third feedback signal from a third carry output of the photonic adder;

generate a photonic sum value, based on the pair of photonic sum values and the third feedback signal; and

provide the photonic sum value to the second set of one or more photonic adders.

19 . The computer-readable storage medium of claim 14 , wherein each of the at least one first photonic adder and the at least one second photonic adder includes one or more nonlinear XOR photonic gates, the one or more nonlinear XOR photonic gates comprises a cascaded connection of at least one of: one or more photonic combiners, one or more beam splitters, one or more nonlinear amplitude thresholders, and one or more phase shifters.

20 . A method comprising:

generating, by one or more photonic input circuits of a photonic processor, one or more photonic output values based on one or more photonic input signals;

receiving, by at least one first photonic adder of a first set of one or more photonic adders of the photonic processor, a first feedback signal from a first carry output of the at least one first photonic adder;

generating, by the at least one first photonic adder, a photonic sum of one or more photonic sums, based at least in part on a portion of the one or more photonic output values and the first feedback signal;

receiving, by at least one second photonic adder of a second set of one or more photonic adders of the photonic processor, a second feedback signal from a second carry output of the at least one second photonic adder; and

generating, by the at least one second photonic adder, an updated version of a photonic input signal of the one or more photonic input signals, based at least in part on a portion of the one or more photonic sums and the second feedback signal.

Assignments (1)

Continuity (1)

References Cited (55)