IP Library › Granted Patent US 12,694,323
Granted Patent B2
US 12,694,323 · App. 18/138,989 · Granted Jul 28, 2026

Systems and methods for degeneracy mitigation in a quantum processor

Inventors: Andrew Douglas King (Vancouver, CA); Alexandre Fréchette (Montreal, CA); Evgeny A. Andriyash (Vancouver, CA); Trevor Michael Lanting (Vancouver, CA); Emile M. Hoskinson (Vancouver, CA); Mohammad H. Amin (Coquitlam, CA)
Assignee: 1372934 B.C. LTD.
G06N10/70G06F15/163G06N10/60
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Quick Facts
Patent No.
US 12,694,323
App. No.
18/138,989
Granted
Jul 28, 2026
Kind
B2
Abstract

Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

Claims (15)

1 . A method of operation of a hybrid computing system that comprises a quantum processor and a digital processor, the quantum processor and the digital processor communicatively coupled to one another, the quantum processor comprising a plurality of qubits, the method comprising:

receiving a pause start and a pause duration by the digital processor as inputs via a user interface;

controlling by the digital processor a quantum annealing evolution performed by the quantum processor, the controlling comprising:

initiating the quantum annealing evolution;

upon reaching the pause start, causing the quantum annealing evolution to pause for the pause duration; and

completing the quantum annealing evolution;

reading out the state of the plurality of qubits by the hybrid computing system.

2 . The method of claim 1 wherein receiving a pause start comprises receiving a measure of progress through the quantum annealing evolution.

3 . The method of claim 1 wherein receiving a pause start and a pause duration comprises receiving a pause start and a pause duration via an Application Programming Interface.

4 . The method of claim 1 wherein controlling by the digital processor a quantum annealing evolution performed by the quantum processor comprises controlling by the digital processor a quantum annealing evolution performed by a plurality of superconducting flux qubits.

5 . The method of claim 1 wherein causing the quantum annealing evolution to pause for the pause duration comprises selecting a subset of qubits, causing the quantum annealing evolution to pause for one or more qubits not in the subset of qubits, and reverse annealing the subset of qubits while the one or more qubits are paused.

6 . The method of claim 1 wherein receiving a pause start and a pause duration by the digital processor comprises receiving more than one pause start and pause duration and wherein the controlling comprises upon reaching each pause start, causing the quantum annealing evolution to pause for the respective pause duration.

7 . The method of claim 1 wherein receiving a pause start and a pause duration by the digital processor as inputs via a user interface further comprises receiving an annealing time and wherein initiating the quantum annealing evolution comprises initiating the quantum annealing evolution in accordance with the annealing time.

8 . The method of claim 1 wherein receiving a pause start and a pause duration by the digital processor as inputs via a user interface further comprises receiving one or more annealing ramp starts and annealing ramp durations and wherein upon reaching the annealing ramp start, causing the quantum annealing evolution to ramp for the annealing ramp duration.

9 . The method of claim 5 , further comprising: forward annealing the subset of qubits after reverse annealing the subset of qubits and before completing the quantum annealing evolution.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2026
From: D-WAVE SYSTEMS INC.
To: 1372929 B.C. LTD.
Reel/Frame 075697/0078 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2026
From: 1372929 B.C. LTD.
To: 1372934 B.C. LTD.
Reel/Frame 075697/0123 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2024
From: LANTING, TREVOR MICHAEL; KING, ANDREW DOUGLAS
To: D-WAVE SYSTEMS INC.
Reel/Frame 067184/0016 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2024
From: FRECHETTE, ALEXANDRE; ANDRIYASH, EVGENY A.; HOSKINSON, EMILE M.; AMIN, MOHAMMAD H.
To: D-WAVE SYSTEMS INC.
Reel/Frame 067184/0042 →
Continuity (7)
Continuation 17379172 · Jul 19, 2021
Continuation 15771606 · Oct 27, 2016
Provisional Application 62399764 · Sep 26, 2016
Provisional Application 62331288 · May 3, 2016
Provisional Application 62324210 · Apr 18, 2016
Provisional Application 62247085 · Oct 27, 2015
Related Publication 20230334355A1 · Oct 19, 2023
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