Systems and methods for looping dynamic memory access operations
A DMA engine may process a work queue (WQ) configured to store work queue elements (WQEs). A processor may write a work queue element (WQE) to the WQ, the WQE including a jump_wait indicator. The DMA engine may be configured to enter a jump_pause state in response to processing the WQE and determining that the jump_wait indicator is set. The DMA engine may be configured to identify a one of the WQEs based at least in part on a jump offset in a trigger message. The DMA engine may be configured to enter a run state and to begin processing the one of the WQEs in response to receiving the trigger message. The DMA engine may be configured to transfer a block of data between a memory and a network interface in response to processing the one of the WQEs.
1 . A system comprising:
a direct memory access (DMA) engine configured to process a work queue (WQ) that is configured to store a plurality of work queue elements (WQEs); and
a processor configured to write a work queue element (WQE) to the WQ, the WQE including a jump_wait indicator;
wherein:
the DMA engine is configured to enter a jump_pause state in response to processing the WQE and determining that the jump_wait indicator is set;
the DMA engine is configured to identify one of the WQEs based at least in part on a jump offset in a trigger message;
the DMA engine is configured to enter a run state and to begin processing the one of the WQEs in response to receiving the trigger message; and
the DMA engine is configured to transfer a block of data between a memory and a network interface in response to processing the one of the WQEs.
2 . The system of claim 1 , wherein:
the DMA engine is configured to process the WQ while in the run state by sequentially processing the WQEs in the WQ.
3 . The system of claim 1 , wherein:
the DMA engine is configured to send an outgoing trigger message in response to determining that the WQE includes a read offset.
4 . The system of claim 1 , further including:
an E-shim that includes the DMA engine,
wherein:
the E-shim is connected to the network interface and to a top level network (TLN);
the E-shim is configured to communicate with a second E-shim via the network interface; and
the E-shim is configured to write blocks of data to the memory via the TLN.
5 . The system of claim 4 , further including:
an M-shim connected to the TLN and to a memory controller,
wherein the M-shim is configured to receive the blocks of data via the TLN and to write the blocks of data to the memory via the memory controller.
6 . The system of claim 1 wherein a coarse-grained reconfigurable (CGR) processor (CGRP) includes an E-shim, an M-shim, and a TLN.
7 . The system of claim 1 further including:
an M-shim configured to communicate with the DMA engine via a top level network (TLN) and to communicate with the memory via a memory controller,
wherein the M-shim is configured to receive blocks of data via the TLN and to write the blocks of data to the memory via the memory controller.
8 . The system of claim 1 wherein the processor includes a coarse-grained reconfigurable (CGR) array.
9 . The system of claim 8 further including:
a top level network (TLN) that includes a first TLN switch; and
an M-shim connected to the TLN and connected to the memory via a memory controller,
wherein the CGR array is configured to access the memory via the first TLN switch.
10 . The system of claim 8 further including:
a top level network (TLN) that includes a second TLN switch; and
an E-shim connected to the TLN,
wherein:
the E-shim includes the DMA engine; and
the CGR array is configured to access the DMA engine via the second TLN switch.
11 . The system of claim 10 further including:
a first TLN switch; and
an M-shim connected to the TLN and connected to the memory via a memory controller,
wherein the CGR array is configured to access the memory via the first TLN switch.
12 . The system of claim 11 wherein the DMA engine is configured to communicate with the memory via the first TLN switch and the second TLN switch.
13 . The system of claim 11 further including a CGR processor (CGRP) that includes the E-shim, the M-shim, the TLN, and the CGR array.
14 . The system of claim 13 wherein the CGRP is configured to implement the WQ.
15 . A coarse-grained reconfigurable (CGR) processor (CGRP) comprising:
a direct memory access (DMA) engine configured to process a work queue (WQ) that is configured to store a plurality of work queue elements (WQEs); and
a processor configured to write a work queue element (WQE) to the WQ, the WQE including a jump_wait indicator, wherein:
the DMA engine is configured to enter a jump_pause state in response to processing the WQE and determining that the jump_wait indicator is set;
the DMA engine is configured to identify one of the WQEs based at least in part on a jump offset in a trigger message; and
the DMA engine is configured to enter a run state and to begin processing the one of the WQEs in response to receiving the trigger message.
16 . The CGRP of claim 15 wherein:
the DMA engine is configured to send an outgoing trigger message in response to determining that the WQE includes a read offset.
17 . A method implemented by a direct memory access (DMA) engine, the method comprising:
reading a work queue element (WQE) that is in a work queue configured to store a plurality of WQEs;
entering a jump_pause state in response to processing the WQE and determining that a jump_wait indicator in the WQE is set;
using a jump offset included in a trigger message to identify one of the WQEs in response to receiving the trigger message; and
entering a run state and beginning to process the one of the WQEs in response to receiving the trigger message.
18 . The method of claim 17 , wherein:
the DMA engine is configured to transfer a block of data between a memory and a network interface in response to processing the one of the WQEs.
19 . The method of claim 17 , wherein:
the DMA engine is configured to process the WQ while in the run state by sequentially processing the WQEs in the WQ.
20 . The method of claim 17 wherein:
the DMA engine is configured to send an outgoing trigger message in response to determining that the WQE includes a read offset.