Output circuitry for analog neural memory in a deep learning artificial neural network
Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In some embodiments, a common mode circuit is used with differential cells, W+ and W−, that together store a weight, W. The common mode circuit can utilize current sources, variable resistors, or transistors as part of the structure for introducing a common mode voltage bias.
1 . An output current neuron circuit, comprising:
a first bit line coupled to a W+ cell in a memory array to draw a first current during a read operation;
a second bit line coupled to a W− cell in the memory array to draw a second current during a read operation, wherein a difference between a value stored in the W+ cell and a value stored in the W− cell is a weight value, W;
a bias circuit to generate a common mode bias voltage;
a first variable current source to apply a first common mode bias current to the first bit line in response to the common mode bias voltage to generate a first output; and
a second variable current source to apply a second common mode bias current to the second bit line in response to the common mode bias voltage to generate a second output, wherein the first and second common mode bias currents are identical;
wherein the first output equals the common mode bias current minus the first current and the second output equals the common mode bias current minus the second current.
2 . The output current neuron circuit of claim 1 , wherein the first variable current source comprises a first PMOS transistor.
3 . The output current neuron circuit of claim 2 , wherein the second variable current source comprises a second PMOS transistor.
4 . An output current neuron circuit, comprising:
a current source;
a bias circuit to apply a control voltage to the current source;
a first variable resistor comprising a first end and a second end, the first end coupled to the current source;
a second variable resistor comprising a third end and a fourth end, the third end coupled to the current source, the current source to provide a bias current to the first variable resistor and the second variable resistor so as to generate a common mode voltage;
a first bit line coupled to a W+ cell during a read operation;
a second bit line coupled to a W− cell during the read operation, wherein a difference between a value stored in the W+ cell and a value stored in the W− cell is a weight value, W;
a first output coupled to the second end of the first variable resistor and the first bit line to provide a first output current; and
a second output coupled to the fourth end of the second variable resistor and the second bit line to provide a second output current, the first output and the second output forming a common mode, differential current signal.
5 . The circuit of claim 4 , wherein the first variable resistor comprises an NMOS transistor, where a voltage applied to a gate of the NMOS transistor determines a resistance of the NMOS transistor.
6 . The circuit of claim 5 , wherein the second variable resistor comprises a second NMOS transistor, where a voltage applied to a gate of the second NMOS transistor determines the resistance of the NMOS transistor.
7 . An output current neuron circuit, comprising:
a first output node to receive a first current from a memory array;
a second output node to receive a second current from a memory array;
a bias circuit to generate a bias current;
a first device to generate a first output current equal to the first current subtracted from the bias current; and
a second device to generate a second output current equal to the second current subtracted from the bias current.
8 . The output current neuron circuit of claim 7 , wherein the first current is generated from a read operation of a bit line coupled to one or more W+ cells.
9 . The output current neuron circuit of claim 8 , wherein the second current is generated from a read operation of a bit line coupled to one or more W− cells.
10 . An output current neuron circuit, comprising:
a first output node to receive a first current from a memory array;
a second output node to receive a second current from a memory array;
a bias circuit to generate a bias voltage at a bias node;
a first variable resistor coupled between the bias node and the first output node; and
a second variable resistor coupled between the bias node and the second output node.
11 . An output block, comprising:
an output current neuron circuit, comprising:
a first bit line coupled to a W+ cell in a memory array to draw a first current during a read operation; and
a second bit line coupled to a W− cell in the memory array to draw a second current during the read operation;
a first bias current coupled to the first bit line; and
a first output current which is proportional to a difference between the first and second current;
wherein the first output current is equal to half of the difference between the first and second current.
12 . An output block, comprising:
an output current neuron circuit, comprising:
a first bit line coupled to a W+ cell in a memory array to draw a first current during a read operation; and
a second bit line coupled to a W− cell in the memory array to draw a second current during the read operation;
a first bias current coupled to the first bit line;
a first output current which is proportional to a difference between the first and second current; and
a second output current that is complementary to the first output current.