Circuit, method, and apparatus for acquiring resistance values of multiple resistors of target system
A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire 1 , a second interconnect parasitic resistor Rwire 2 , an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire 1 and one end of the Rnet. The other end of the Rwire 1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire 2 . A positive electrode of the Dio_die is connected to the other end of the Rnet.
1 . A circuit comprising: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire 1 , a second interconnect parasitic resistor Rwire 2 , an encapsulation network resistor Rnet, a first diode Dio_VDD, a second diode Dio_Vss, and a third diode Dio_die, wherein
the working voltage node resistor Rb is respectively connected to one end of the first interconnect parasitic resistor Rwire 1 and one end of the encapsulation network resistor Rnet; the other end of the first interconnect parasitic resistor Rwire 1 is connected to a negative electrode of the first diode Dio_VDD, and a positive electrode of the first diode Dio_VDD is respectively connected to the reference node resistor Ra and a negative electrode of the second diode Dio_Vss; a positive electrode of the second diode Dio_VSS is respectively connected to the common ground voltage node resistor Rc and a negative electrode of the third diode Dio_die via the second interconnect parasitic resistor Rwire 2 ; and a positive electrode of the third diode Dio_die is connected to the other end of the encapsulation network resistor Rnet.
2 . The circuit according to claim 1 , wherein the working voltage node resistor Rb is a first array resistor composed of multiple resistors connected in parallel to each other.
3 . The circuit according to claim 1 , wherein the common ground voltage node resistor Rc is a second array resistor composed of multiple resistors connected in parallel to each other.
4 . The circuit according to claim 1 , wherein the working voltage node resistor Rb is connected to one end of the first interconnect parasitic resistor Rwire 1 and one end of the encapsulation network resistor Rnet through at least one diode.
5 . The circuit according to claim 1 , wherein the reference node resistor Ra comprises a third array resistor, wherein the third array resistor is composed of multiple resistors connected in parallel to each other.
6 . The circuit according to claim 1 , wherein
the working voltage node resistor Rb, the common ground voltage node resistor Rc, and the reference node resistor Ra are all bumps on a circuit substrate.
7 . The circuit according to claim 1 , wherein the positive electrode of the second diode Dio_Vss is connected to one end of the second interconnect parasitic resistor Rwire 2 , and the other end of the second interconnect parasitic resistor Rwire 2 is respectively connected to the common ground voltage node resistor Rc and a negative electrode of the third diode Dio_die.
8 . A resistance value acquisition method based on a circuit comprising a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire 1 , a second interconnect parasitic resistor Rwire 2 , an encapsulation network resistor Rnet, a first diode Dio_VDD, a second diode Dio_Vss, and a third diode Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the first interconnect parasitic resistor Rwire 1 and one end of the encapsulation network resistor Rnet; the other end of the first interconnect parasitic resistor Rwire 1 is connected to a negative electrode of the first diode Dio_VDD, and a positive electrode of the first diode Dio_VDD is respectively connected to the reference node resistor Ra and a negative electrode of the second diode Dio_Vss; a positive electrode of the second diode Dio_VSS is respectively connected to the common ground voltage node resistor Rc and a negative electrode of the third diode Dio_die via the second interconnect parasitic resistor Rwire 2 ; and a positive electrode of the third diode Dio_die is connected to the other end of the encapsulation network resistor Rnet, the method comprising:
determining nodes based on multiple resistors in the circuit, and selecting any two nodes as a node combination, wherein the multiple resistors at least comprise the working voltage node resistor Rb, the common ground voltage node resistor Rc, and the reference node resistor Ra;
applying different voltage polarities between the two nodes of the node combination to perform voltage and current characteristic detection, and acquiring a series resistance value between the two nodes of the node combination under each of the different voltage polarities; and
acquiring resistance values of the multiple resistors in the circuit based on the series resistance value.
9 . The method according to claim 8 , wherein the third diode Dio_die is an integrated diode on a Si Die, and the method further comprises:
exerting a stress with a preset duration and a preset strength to the Si Die;
when the preset duration reaches a first threshold or the preset strength reaches a second threshold, stopping exerting the stress;
testing the Si Die, and calculating the resistance values of the multiple resistors; and
determining an expected life value of the Si Die based on the calculated resistance values of the multiple resistors.
10 . The method according to claim 8 , wherein the working voltage node resistor Rb is a first array resistor composed of multiple resistors connected in parallel to each other.
11 . The method according to claim 8 , wherein the common ground voltage node resistor Rc is a second array resistor composed of multiple resistors connected in parallel to each other.
12 . The method according to claim 8 , wherein the working voltage node resistor Rb is connected to one end of the first interconnect parasitic resistor Rwire 1 and one end of the encapsulation network resistor Rnet through at least one diode.
13 . The method according to claim 8 , wherein the reference node resistor Ra comprises a third array resistor, wherein the third array resistor is composed of multiple resistors connected in parallel to each other.
14 . The method according to claim 8 , wherein the working voltage node resistor Rb, the common ground voltage node resistor Rc, and the reference node resistor Ra are all bumps on a circuit substrate.
15 . The method according to claim 8 , wherein the positive electrode of the second diode Dio_Vss is connected to one end of the second interconnect parasitic resistor Rwire 2 , and the other end of the second interconnect parasitic resistor Rwire 2 is respectively connected to the common ground voltage node resistor Rc and a negative electrode of the third diode Dio_die.
16 . A non-transitory computer-readable storage medium storing a computer program, wherein the computer program is configured to perform, at runtime, the operations in the method according to claim 8 .
17 . A resistance value acquisition apparatus based on a circuit comprising a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire 1 , a second interconnect parasitic resistor Rwire 2 , an encapsulation network resistor Rnet, a first diode Dio_VDD, a second diode Dio_Vss, and a third diode Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the first interconnect parasitic resistor Rwire 1 and one end of the encapsulation network resistor Rnet; the other end of the first interconnect parasitic resistor Rwire 1 is connected to a negative electrode of the first diode Dio_VDD, and a positive electrode of the first diode Dio_VDD is respectively connected to the reference node resistor Ra and a negative electrode of the second diode Dio_Vss; a positive electrode of the second diode Dio_VSS is respectively connected to the common ground voltage node resistor Rc and a negative electrode of the third diode Dio_die via the second interconnect parasitic resistor Rwire 2 ; and a positive electrode of the third diode Dio_die is connected to the other end of the encapsulation network resistor Rnet, the apparatus comprising a memory storing instructions and a processor in communication with the memory, wherein the processor is configured to execute the instructions to:
determine nodes based on multiple resistors in the circuit, and select any two nodes as a node combination, wherein the multiple resistors at least comprise the working voltage node resistor Rb, the common ground voltage node resistor Rc, and the reference node resistor Ra;
apply different voltage polarities between the two nodes of the node combination to perform voltage and current characteristic detection, and acquire a series resistance value between the two nodes of the node combination under each of the different voltage polarities; and
acquire resistance values of the multiple resistors in the circuit based on the series resistance value.
18 . The apparatus according to claim 17 , wherein the third diode Dio_die is an integrated diode on a Si Die, and the processor is further configured to execute the instructions to:
exert a stress with a preset duration and a preset strength to the Si Die;
when the preset duration reaches a first threshold or the preset strength reaches a second threshold, stopping exerting the stress;
testing the Si Die, and calculating the resistance values of the multiple resistors; and
determining an expected life value of the Si Die based on the calculated resistance values of the multiple resistors.