SAR ADC bit storage upon reset

1 . A system comprising:

a successive approximation register (SAR) analog-to-digital converter (ADC) configured to perform operations comprising:

receiving an analog signal;

receiving a first instance of conversion trigger signal;

in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;

while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal; and

temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.

2 . The system of claim 1 , wherein the second instance of the conversion trigger signal is received prior to the SAR ADC completing generation of the set of digital bit values corresponding to the analog signal.

3 . The system of claim 1 , wherein the SAR ADC comprises a comparator, and wherein the second instance of the conversion trigger signal is received prior to the comparator resolving the one or more digital bit values, the first and second instances of the conversion trigger signal causing the comparator to be reset.

4 . The system of claim 3 , wherein the one or more bits comprise a least significant bit (LSB) of the analog signal.

5 . The system of claim 3 , the operations comprising:

while the comparator is being reset by the second instance of the conversion trigger signal, latching the one or more bits generated by the comparator.

6 . The system of claim 5 , comprising:

an edge-sensitive set-reset (SR) latch coupled to receive the one or more digital bit values from the comparator.

7 . The system of claim 6 , wherein a reset input of the SR latch is coupled to receive the second instance of the conversion trigger signal, and wherein a set input of the SR latch is coupled to receive the one or more digital bit values of the comparator.

8 . The system of claim 7 , wherein the one or more digital bit values of the comparator are temporarily stored by the SR latch in response to detecting a transition of the second instance of the conversion trigger signal.

9 . The system of claim 8 , wherein the transition comprises a rising edge of the second instance of the conversion trigger signal.

10 . The system of claim 8 , comprising:

a transparent latch coupled to an output of the SR latch, the transparent latch comprising a latch input coupled to the output of the SR latch and a reset input coupled to the second instance of the conversion trigger signal.

11 . The system of claim 10 , wherein the second instance of the conversion trigger signal is passed through an inventor to the reset inputs of the transparent latch and the SR latch.

12 . The system of claim 10 , wherein an output of the transparent latch holds the one or more digital bit values after the comparator is reset by the second instance of the conversion trigger signal.

13 . The system of claim 5 , a flip-flop coupled to receive the one or more bits from the comparator, the flip-flop being triggered to store the one or more digital bit values from the comparator in response to detecting a transition of the second instance of the conversion trigger signal.

14 . The system of claim 1 , wherein the temporarily stored one or more digital bit values are combined with prior conversion results to form an output of the SAR ADC comprising the set of digital bit values.

15 . The system of claim 1 , wherein the SAR ADC comprises:

a comparator that generates the set of digital bit values based on a comparison of a received voltage signal value to a reference voltage;

one or more buffers coupled to an output of the comparator;

a digital-to-analog converter (DAC) coupled to an output of the one or more buffers via logic, the DAC configured to generate the reference voltage based on a current comparison of the comparator.

16 . The system of claim 15 , wherein the comparator is reset in response to a strobe signal generated by a strobe generator, the strobe generator providing the strobe signal for each instance of the conversion trigger signal.

17 . A method comprising:

receiving, by a successive approximation register (SAR) analog-to-digital converter (ADC), an analog signal;

receiving a first instance of conversion trigger signal;

in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;

while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal; and

temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.

18 . The method of claim 17 , wherein the second instance of the conversion trigger signal is received prior to the SAR ADC completing generation of the set of digital bit values corresponding to the analog signal.

19 . A non-transitory computer-readable medium comprising computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

receiving, by a successive approximation register (SAR) analog-to-digital converter (ADC), an analog signal;

receiving a first instance of conversion trigger signal;

in response to receiving the first instance of the conversion trigger signal, generating a set of digital bit values corresponding to the analog signal;

while one or more digital bit values corresponding to the analog signal are being generated, receiving a second instance of the conversion trigger signal; and

temporarily storing the one or more digital bit values in response to receiving the second instance of the conversion trigger signal.

20 . The non-transitory computer-readable medium of claim 19 , wherein the second instance of the conversion trigger signal is received prior to the SAR ADC completing generation of the set of digital bit values corresponding to the analog signal.