Loopback test for phase interpolator codes
Loopback testing of a phase interpolator (PI) in a serial link system. A CDR loop operates in a loopback mode until a sampling clock signal locks to a first valid lock point in a first UI. The CDR loop includes the PI and a phase blender for blending weights of multiple clock signals, phase offset from each other, to apply a blender delay to the sampling clock signal. The PI phase code is stored, and the sampled loopback signal is checked for bit errors. The blender delay is repeatedly adjusted to phase shift the sampling clock signal, locking the sampling clock signal with the CDR loop, and checking for bit errors of the loopback signal, such that the blender delay sweeps across at least one UI. For each further UI, the PI phase code is adjusted to target a further valid lock point, and the blender delay is swept.
1 . A method for loopback self-testing of a phase interpolator (PI) in a serial link system, the method comprising:
operating a clock and data recovery (CDR) loop in a loopback mode until a sampling clock signal locks to a first valid lock point in a first unit interval (UI) of a loopback signal, the CDR loop comprising:
the PI; and
a phase blender for blending weights of multiple clock signals phase offset from each other to apply a blender delay to the sampling clock signal;
storing a PI phase code corresponding to a phase adjustment of the locked sampling clock signal;
checking for bit errors of the loopback signal as sampled by the locked sampling clock signal;
sweeping the blender delay by repeating one or more times:
adjusting the blender delay of the phase blender to phase shift the sampling clock signal;
operating the CDR loop to lock the sampling clock signal; and
checking for bit errors,
such that values of the blender delay span at least one UI of phase; and
sweeping across one or more further UIs by repeating, for each further UI:
adjusting the PI phase code to target a further valid lock point in the further UI; and
sweeping the blender delay.
2 . The method of claim 1 , wherein:
the adjusting of the blender delay comprises adjusting the blender delay by a blender step spanning a phase that is no greater than a dither range of the CDR loop.
3 . The method of claim 2 , further comprising:
prior to operating the CDR loop in the loopback mode, adjusting a bandwidth of the CDR loop to adjust the dither range.
4 . The method of claim 2 , wherein:
the one or more further UIs consists of three further UIs, such that the method checks for bit errors when locked to four valid lock points over four UIs.
5 . The method of claim 1 , wherein:
the blending of the weights of the multiple clock signals comprises:
blending outputs of two or more blending buffers to weight multiple input phases to create an output phase that is a combination of the input phases, the blender delay being based on the output phase.
6 . The method of claim 1 , wherein:
the PI comprises an injection-locked ring to generate multiple clock phases using constant step sizes; and
the phase blender blends the multiple clock phases to generate blended clock phases.
7 . The method of claim 5 , wherein:
the blending buffers provide a blending range enabling the values of the blender delay to span at least 1.5 UIs.
8 . The method of claim 1 , wherein:
the CDR loop further comprises a CDR circuit configured to control the PI to maintain a lock of the sampling clock signal on the loopback signal; and
the CDR loop causes the PI phase code to dither by 4 or 5 codes when locked.
9 . The method of claim 1 , wherein:
the operating of the CDR loop in the loopback mode comprises:
routing a transmitter built-in self-test data signal through a transmitter serializer and a transmitter driver to generate the loopback signal.
10 . The method of claim 9 , wherein:
the operating of the CDR loop in the loopback mode further comprises:
providing the loopback signal to a receive path comprising a continuous time linear equalizer (CTLE), an analog-to-digital converter (ADC), and a feed-forward equalizer (FFE).
11 . A system for performing loopback self-testing of a phase interpolator (PI) in a serial link system, the system comprising:
a clock and data recovery (CDR) loop to operate in a loopback mode until a sampling clock signal locks to a first valid lock point in a first unit interval (UI) of a loopback signal, the CDR loop comprising:
the PI;
a phase blender for blending weights of multiple clock signals phase offset from each other to apply a blender delay to the sampling clock signal; and
a memory for storing a PI phase code corresponding to a phase adjustment of the locked sampling clock signal;
a built-in self-test (BIST) circuit checking for bit errors of the loopback signal as sampled by the locked sampling clock signal; and
control logic to perform operations comprising:
sweeping the blender delay by repeating one or more times:
adjusting the blender delay of the phase blender to phase shift the sampling clock signal;
operating the CDR loop to lock the sampling clock signal; and
checking for bit errors,
such that values of the blender delay span at least one UI of phase; and
sweeping across one or more further UIs by repeating, for each further UI:
adjusting the PI phase code to target a further valid lock point in the further UI; and
sweeping the blender delay.
12 . The system of claim 11 , wherein:
the blender control circuit adjusts the blender delay by a blender step spanning a phase that is no greater than a dither range of the CDR loop.
13 . The system of claim 12 , the operations further comprising:
prior to operating the CDR loop in the loopback mode, adjusting a bandwidth of the CDR loop to adjust the dither range.
14 . The system of claim 12 , wherein:
the one or more further UIs consists of three further UIs, such that the BIST circuit checks for bit errors when locked to four valid lock points over four UIs.
15 . The system of claim 11 , wherein:
the blending of the weights of the multiple clock signals comprises:
blending outputs of two or more blending buffers to weight multiple input phases to create an output phase that is a combination of the input phases, the blender delay being based on the output phase.
16 . The system of claim 11 , wherein:
the PI comprises an injection-locked ring to generate multiple clock phases using constant step sizes; and
the phase blender blends the multiple clock phases to generate blended clock phases.
17 . The system of claim 11 , wherein:
the CDR loop further comprises a CDR circuit configured to control the PI to maintain a lock of the sampling clock signal on the loopback signal; and
the CDR loop causes the PI phase code to dither by 4 or 5 codes when locked.
18 . The system of claim 11 , wherein:
the operating of the CDR loop in the loopback mode comprises:
routing a transmitter built-in self-test data signal through a transmitter serializer and a transmitter driver to generate the loopback signal.
19 . The system of claim 18 ,
further comprising a receive path comprising:
a continuous time linear equalizer (CTLE);
an analog-to-digital converter (ADC); and
a feed-forward equalizer (FFE);
wherein:
the operating of the CDR loop in the loopback mode further comprises:
providing the loopback signal to the receive path.
20 . A system for performing loopback self-testing of a phase interpolator (PI) in a serial link system, the system comprising:
a phase-locked loop for generating a sampling clock signal;
a clock and data recovery (CDR) loop to operate in a loopback mode until a sampling clock signal locks to a first valid lock point in a first unit interval (UI) of a loopback signal, the CDR loop comprising:
an analog-to-digital converter (ADC);
a feed-forward equalizer (FFE);
the PI;
a phase blender for blending weights of multiple clock signals phase offset from each other to apply a blender delay to the sampling clock signal; and
a memory for storing a PI phase code corresponding to a phase adjustment of the locked sampling clock signal;
a built-in self-test (BIST) circuit checking for bit errors of the loopback signal as sampled by the locked sampling clock signal;
a transmitter path comprising a transmitter serializer and a transmitter driver;
a continuous time linear equalizer (CTLE) for receiving the loopback signal from the transmitter path and equalizing the received loopback signal; and
control logic operable to perform operations comprising:
sweeping the blender delay by repeating one or more times:
adjusting the blender delay of the phase blender to phase shift the sampling clock signal;
operating the CDR loop to lock the sampling clock signal; and
checking for bit errors,
such that values of the blender delay span at least one UI of phase; and
sweeping across one or more further UIs by repeating, for each further UI:
adjusting the PI phase code to target a further valid lock point in the further UI; and
sweeping the blender delay.