Systems and methods for deploying frame-based simulation models on programmable logic devices
Systems and methods transform frame-based algorithms into revised algorithms having the same behavior as the frame-based algorithms, but that can be synthesized in hardware. The frame-based algorithm may be represented by an executable simulation model, such as a block diagram model.
1 . A computer-implemented method comprising:
accessing an executable simulation model configured to receive frame-based input data, wherein the executable simulation model includes (i) one or more frame-based signals having a datatype and a rate and (ii) a component configured to perform one or more frame-based operations and produce frame-based output data, the component performing at least one of an elementwise operation, a neighborhood operation, a reduction operation, an iteration operation, a structured access operation, or a random access operation;
generating, by one or more processors, hardware description language (HDL) code for the executable simulation model, wherein the generating the HDL code includes:
updating the datatype of the one or more frame-based signals to a new datatype;
updating the rate of the one or more frame-based signals to a new rate;
converting the frame-based input data to streaming input data;
converting the frame-based output data to streaming output data;
converting the one or more frame-based signals to one or more streaming signals;
converting the component performing the at least one of the elementwise operation, the neighborhood operation, the reduction operation, the iteration operation, the structured access operation, or the random access operation to a sample-based implementation operating on the one or more streaming signals;
inserting first logic for generating a ready signal indicating the converted component is ready to process input data;
inserting second logic for generating a data valid signal indicating output data computed by the converted component is valid;
adding an input buffer and an output buffer;
configuring the input buffer to receive the streaming input data and to provide the streaming input data to the converted component in response to the ready signal; and
configuring the output buffer to store the output data in response to the data valid signal and to provide the output data as the streaming output data.
2 . The computer-implemented method of claim 1 wherein the new datatype and the new rate are based on a samples per hardware execution cycle parameter.
3 . The computer-implemented method of claim 1 wherein the component performs the neighborhood operation and the neighborhood operation defines a neighborhood and a filter, the method further comprising:
inserting third logic for counting elements of the streaming input data to construct the neighborhood at the converted component.
4 . The computer-implemented method of claim 1 wherein the executable simulation model includes (i) a second component configured to perform one or more second frame-based operations and produce second frame-based output data and (ii) one or more second frame-based signals having a second datatype and a second rate, the method further comprising:
creating separate partitions for the component and the second component; updating the second datatype of the one or more second frame-based signals to a new second datatype based on a samples per hardware execution cycle parameter;
updating the second rate of the one or more second frame-based signals to a new second rate as a function of the samples per hardware execution cycle parameter;
converting the one or more second frame-based signals to one or more second streaming signals;
converting the second component to a sample-based implementation;
inserting second logic associated with the second component, wherein the second logic is configured to (i) buffer second data from the one or more streaming signals and (ii) process one or more valid signals; and
connecting the one or more valid signals of the inserted second logic to the second component.
5 . The computer-implemented method of claim 1 wherein the input buffer and the output buffer are First In First Out (FIFO) buffers.
6 . The computer-implemented method of claim 1 wherein the executable simulation model performs image processing and the frame-based input data is at least one of 240×320 pixels, 640×480 pixels, 1280×720 pixels, 1920×1080 pixels, 3840×2160 pixels, 4096×2160 pixels, or 7680×4320 pixels.
7 . The computer-implemented method of claim 1 wherein the frame-based input data is one-dimensional (1D) vector data, two-dimensional (2D) matrix data, or multi-dimensional matrix data.
8 . The computer-implemented method of claim 1 wherein the executable simulation model performs signal processing on wireless signals, radar signals, or lidar signals.
9 . The computer-implemented method of claim 1 further comprising:
utilizing the generated HDL code to synthesize a programmable logic device.
10 . The computer-implemented method of claim 9 wherein the programmable logic device has Input-Output (IO) resources and a size of the frame-based input data exceeds the IO resources of the programmable logic device.
11 . The computer-implemented method of claim 10 wherein a size of the one or more streaming signals is within the IO resources of the programmable logic device.