High-speed octal-rate wireline transmitters
A transmitter includes a multiplexer configured to receive and process an N-bit data stream, where N is an even number. The multiplexer includes N pulse generator circuits that generate N pulse signals in N different phases of a duty cycle. The transmitter further includes a driver and an output pad connected to an output of the driver, serving as an interface between the transmitter and a transmission medium. The driver includes a first set of N transistors and a second set of N/2 transistors, configured to receive the N pulse signals as inputs to output a single bit data stream. An output of the driver is electrically coupled with the output pad.
1 . A transmitter, comprising:
a multiplexer configured to receive and process an N-bit data stream, wherein N is an even number, the multiplexer comprising:
a set of N pulse generator circuits configured to receive the N-bit data stream to output N pulse signals in N different phases of a duty cycle, each of the pulse generator circuits comprising a NAND gate, an inverter, and a NOR gate, wherein the NAND gate receives a data signal and a first clock signal as inputs to generate a first output, the inverter receives a second clock signal as input to generate a second output, the NOR gate receives the first output and the second output as inputs to generate a third output, and the third output is an output of the pulse generator circuit that is received by a driver;
the driver configured to receive the N pulse signals as inputs to output a single-bit data stream, the driver comprising a first set of N transistors, acting as switches and a second set of N/2 transistors acting as current sources; and
an output pad electrically coupled with an output of the driver, serving as an interface between the transmitter and a transmission medium, wherein
a gate of each transistor in the first set is configured to receive one of the N pulse signals,
a source of each transistor in the second set is electrically coupled with drains of a corresponding pair of transistors in the first set, and
drains of the transistors in the second set electrically coupled with the output pad.
2 . The transmitter of claim 1 , wherein the multiplexer is a first multiplexer, the driver is a first driver, the output pad is a first output pad, the N-bit data stream is a first N-bit data stream, and the single-bit data stream is a first single-bit data stream,
wherein the transmitter further comprises a second multiplexer identical to the first multiplexer, a second driver identical to the first driver, and a second output pad identical to the first output pad,
wherein the second multiplexer is configured to receive and process a second N-bit data stream that is in opposite phase of the first N-bit data stream, and
wherein the second driver is configured to output a second single-bit data stream that is in opposite phase of the first single-bit data stream.
3 . The transmitter of claim 1 , wherein N is equal to 6 or 8.
4 . The transmitter of claim 1 , wherein the third output is a voltage signal, and the driver is a current mode driver configured to convert the voltage signal into a current signal.
5 . The transmitter of claim 1 , the transmitter further comprising a clock generator configured to generate N-phase clock signals, each of which is evenly spaced apart in a duty cycle,
wherein the N-phase clock signals are input to the multiplexer as timing references for facilitating selecting of one of the N-bit data stream.
6 . The transmitter of claim 5 , wherein N is equal to 8, the N-phase clock signals comprise:
a first clock signal at 0 degree;
a second clock signal at 45 degrees;
a third clock signal at 90 degrees;
a fourth clock signal at 135 degrees;
a fifth clock signal at 180 degrees;
a sixth clock signal at 225 degrees;
a seventh clock signal at 270 degrees; and
an eighth clock signal at 315 degrees.
7 . The transmitter of claim 5 , the clock generator is configured to generate one of following clock rates: 7 GHz, 14 GHz, 28 GHz, 56 GHz, or 112 GHz.
8 . The transmitter of claim 7 , wherein the transmitter is configured to have a serialization rate that is 16 times of a clock rate generated by the clock generator.
9 . The transmitter of claim 1 , wherein the N-bit data stream or the single-bit data stream is modulated under pulse amplitude modulation 4-level (PAM4) modulation scheme.
10 . A non-transitory computer readable medium storing instructions, which when executed by a processor, cause the processor to simulate or emulate a transmitter, the transmitter comprising:
a multiplexer configured to receive and process an N-bit data stream, wherein N is an even number, the multiplexer comprising:
a set of N pulse generator circuits configured to generate N pulse signals in N different phases of a duty cycle, each of the pulse generator circuits comprising a NAND gate, an inverter, and a NOR gate, wherein the NAND gate receives a data signal and a first clock signal as inputs to generate a first output, the inverter receives a second clock signal as input to generate a second output, the NOR gate receives the first output and the second output as inputs to generate a third output, and the third output is an output of the pulse generator circuit that is received by a driver;
the driver configured to receive the N pulse signals as inputs to output a single-bit data stream, the driver comprising a first set of N transistors and a second set of N/2 transistors, acting as current sources; and
an output pad electrically coupled with an output of the driver, serving as an interface between the transmitter and a transmission medium, wherein
a gate of each transistor in the first set is configured to receive one of the N pulse signals,
a source of each transistor in the second set is electrically coupled with drains of a corresponding pair of transistors in the first set, and
drains of the transistors in the second set are electrically coupled with the output pad.
11 . The non-transitory computer readable medium of claim 10 , wherein the multiplexer is a first multiplexer, the driver is a first driver, the output pad is a first output pad, the N-bit data stream is a first N-bit data stream, and the single-bit data stream is a first single-bit data stream,
wherein the non-transitory computer readable medium further stores additional instructions, which when executed by the processor, cause the processor to simulate a second multiplexer identical to the first multiplexer, a second driver identical to the first driver, and a second output pad identical to the first output pad,
wherein the second multiplexer is configured to receive and process a second N-bit data stream that is in opposite phase of the first N-bit data stream, and
wherein the second driver is configured to output a second single-bit data stream that is in opposite phase of the first single-bit data stream.
12 . The non-transitory computer readable medium of claim 10 , wherein N is equal to 6 or 8.
13 . The non-transitory computer readable medium of claim 10 , each of the pulse generator circuits comprising a NAND gate, an inverter, and a NOR gate, wherein:
the NAND gate receives a data signal and a first clock signal as inputs to generate a first output,
the inverter receives a second clock signal as input to generate a second output,
the NOR gate receives the first output and the second output as inputs to generate a third output, and
the third output is an output of the pulse generator circuit that is received by the driver.
14 . The non-transitory computer readable medium of claim 13 , wherein the third output is a voltage signal, and the driver is a current mode driver configured to convert the voltage signal into a current signal.
15 . The non-transitory computer readable medium of claim 10 , the transmitter further comprising a clock generator configured to generate N-phase clock signals, each of which is evenly spaced apart in a duty cycle,
wherein the N-phase clock signals are input to the multiplexer as timing references for facilitating selecting of one of the N-bit data stream.
16 . The non-transitory computer readable medium of claim 15 , wherein N is equal to 8, the N-phase clock signals comprise:
a first clock signal at 0 degree;
a second clock signal at 45 degrees;
a third clock signal at 90 degrees;
a fourth clock signal at 135 degrees;
a fifth clock signal at 180 degrees;
a sixth clock signal at 225 degrees;
a seventh clock signal at 270 degrees; and
an eighth clock signal at 315 degrees.
17 . The non-transitory computer readable medium of claim 15 , the clock generator is configured to generate one of following clock rates: 7 GHz, 14 GHz, 28 GHz, 56 GHz, or 112 GHz.
18 . The non-transitory computer readable medium of claim 17 , wherein the transmitter is configured to have a serialization rate that is 16 times of a clock rate generated by the clock generator.
19 . The non-transitory computer readable medium of claim 10 , wherein the N-bit data stream or the single-bit data stream is modulated under pulse amplitude modulation 4-level (PAM4) modulation scheme.