Circuit board and fabrication method thereof, and electronic device
This application discloses a circuit board and a fabrication method thereof, and an electronic device. The circuit board includes: a main board; a daughter board disposed in a blind cavity of the main board; and a build-up board, disposed on surfaces of the main board and the daughter board. The build-up board includes a build-up structure containing a plurality of layers. The build-up board is provided with a first chip region, a second chip region, and an interconnection region located between the first chip region and the second chip region. The interconnection region covers a surface of the daughter board. A plurality of interconnection traces are provided in the interconnection region.
1 . A circuit board, comprising:
a main board, wherein the main board is provided with a blind cavity;
a daughter board, wherein the daughter board is disposed in the blind cavity, and a daughter board trace is provided in the daughter board; and
a build-up board, wherein the build-up board is disposed on surfaces of the main board and the daughter board; the build-up board comprises a build-up structure containing a plurality of layers; the build-up board is provided with a first chip region, a second chip region, and an interconnection region located between the first chip region and the second chip region; and the interconnection region covers a surface of the daughter board; and
a plurality of interconnection traces are provided in the interconnection region; each interconnection trace comprises: a first horizontal trace and a second horizontal trace disposed on a same layer of the build-up structure, a first vertical trace disposed in the build-up board and configured to connect the first horizontal trace and the daughter board trace, and a second vertical trace disposed in the build-up board and configured to connect the second horizontal trace and the daughter board trace; a first trace configured to connect the first horizontal trace and a first chip is provided in the first chip region, and a second trace configured to connect the second horizontal trace and a second chip is provided in the second chip region.
2 . The circuit board according to claim 1 , wherein the daughter board trace is a U-shaped structure, the daughter board trace is connected to the first vertical trace by a first pad, and is connected to the second vertical trace by a second pad; and
the first pad and the second pad are located on a surface of the daughter board on a side close to the build-up board.
3 . The circuit board according to claim 2 , wherein the first chip is located on a surface of the first chip region, and the second chip is located on a surface of the second chip region.
4 . The circuit board according to claim 2 , wherein the first chip region is provided with a third trace configured to connect the first chip and the main board, and the second chip region is provided with a fourth trace configured to connect the second chip and the main board.
5 . The circuit board according to claim 1 , wherein the build-up structure comprises prepreg and copper foil stacked sequentially.
6 . The circuit board according to claim 1 , wherein a space between the daughter board and the main board is filled with a dielectric layer.
7 . The circuit board according to claim 6 , wherein the dielectric layer is a resin material layer.
8 . The circuit board according to claim 1 , wherein a plurality of interconnection traces are nested in layers across a plurality of layers of the build-up structure.
9 . A method for fabricating the circuit board according to claim 1 , comprising:
forming the blind cavity on the main board;
disposing, in the blind cavity, the daughter board containing the daughter board trace; and
performing a plurality of build-up processes on a surface of the main board to form the build-up board; performing stacked-via drilling and electroplating on the build-up structure after each build-up process to form a first vertical trace and a second vertical trace; and creating traces for the build-up structure after each build-up process to form a first trace, a second trace, a first horizontal trace, and a second horizontal trace, wherein the first trace, the first horizontal trace, the first vertical trace, the daughter board trace, the second vertical trace, the second horizontal trace, and the second trace are connected sequentially.
10 . The method for fabricating the circuit board according to claim 9 , wherein the daughter board trace is a U-shaped structure, the daughter board trace is connected to the first vertical trace by a first pad, and is connected to the second vertical trace by a second pad; and
the first pad and the second pad are located on a surface of the daughter board on a side close to the build-up board.
11 . The method for fabricating the circuit board according to claim 10 , wherein the first chip is located on a surface of the first chip region, and the second chip is located on a surface of the second chip region.
12 . The method for fabricating the circuit board according to claim 10 , wherein the first chip region is provided with a third trace configured to connect the first chip and the main board, and the second chip region is provided with a fourth trace configured to connect the second chip and the main board.
13 . The method for fabricating the circuit board according to claim 9 , wherein the build-up structure comprises prepreg and copper foil stacked sequentially.
14 . The method for fabricating the circuit board according to claim 9 , wherein a space between the daughter board and the main board is filled with a dielectric layer.
15 . The method for fabricating the circuit board according to claim 14 , wherein the dielectric layer is a resin material layer.
16 . The method for fabricating the circuit board according to claim 1 , wherein a plurality of interconnection traces are nested in layers across a plurality of layers of the build-up structure.
17 . An electronic device, wherein the electronic device comprises the circuit board according to claim 1 .
18 . The electronic device according to claim 17 , wherein the daughter board trace is a U-shaped structure, the daughter board trace is connected to the first vertical trace by a first pad, and is connected to the second vertical trace by a second pad; and
the first pad and the second pad are located on a surface of the daughter board on a side close to the build-up board.
19 . The electronic device according to claim 18 , wherein the first chip is located on a surface of the first chip region, and the second chip is located on a surface of the second chip region.
20 . The electronic device according to claim 18 , wherein the first chip region is provided with a third trace configured to connect the first chip and the main board, and the second chip region is provided with a fourth trace configured to connect the second chip and the main board.
21 . The electronic device according to claim 17 , wherein the build-up structure comprises prepreg and copper foil stacked sequentially.
22 . The electronic device according to claim 17 , wherein a space between the daughter board and the main board is filled with a dielectric layer.
23 . The electronic device according to claim 17 , wherein a plurality of interconnection traces are nested in layers across a plurality of layers of the build-up structure.
24 . An electronic device, wherein the electronic device comprises a circuit board fabricated using the method according to claim 9 .
25 . The electronic device according to claim 24 , wherein the daughter board trace is a U-shaped structure, the daughter board trace is connected to the first vertical trace by a first pad, and is connected to the second vertical trace by a second pad; and
the first pad and the second pad are located on a surface of the daughter board on a side close to the build-up board.
26 . The electronic device according to claim 25 , wherein the first chip is located on a surface of the first chip region, and the second chip is located on a surface of the second chip region.
27 . The electronic device according to claim 25 , wherein the first chip region is provided with a third trace configured to connect the first chip and the main board, and the second chip region is provided with a fourth trace configured to connect the second chip and the main board.
28 . The electronic device according to claim 24 , wherein the build-up structure comprises prepreg and copper foil stacked sequentially.
29 . The electronic device according to claim 24 , wherein a space between the daughter board and the main board is filled with a dielectric layer.
30 . The electronic device according to claim 24 , wherein a plurality of interconnection traces are nested in layers across a plurality of layers of the build-up structure.