Memory data inversion
An example is a circuit including a memory output block having a single bit width output node. The memory output block includes a memory bank and a logic inversion circuit. The memory bank is configured to output a read datum. The logic inversion circuit is associated with the memory bank. An input node of the logic inversion circuit is electrically coupled to the memory bank to receive the read datum. The logic inversion circuit is configured to output an output datum on an output node of the logic inversion circuit. The logic inversion circuit is configured to obtain the output datum by selecting either one of an inverted version of the read datum or a non-inverted version of the read datum received from the memory bank based on a column of the memory bank from which the read datum is read.
1 . A circuit comprising:
a memory output block having a single bit width output node, the memory output block comprising:
a first memory bank having a first plurality of columns, wherein a first column of the first plurality of columns has a first plurality of memory cells, each memory cell of the first plurality of memory cells being configured to store a respective first stored datum; and
a first logic inversion circuit associated with the first memory bank, an input node of the first logic inversion circuit being electrically coupled to the first memory bank to receive the respective first stored datum,
wherein the first logic inversion circuit is configured to output a respective first output datum by selecting either one of an inverted version of the respective first stored datum or a non-inverted version of the respective first stored datum for all of the first plurality of memory cells based on the first column of the first memory bank.
2 . The circuit of claim 1 , wherein the memory output block further includes:
a second memory bank having a second plurality of columns, wherein a second column of the second plurality of columns has a second plurality of memory cells, each memory cell of the second plurality of memory cells being configured to store a respective second stored datum; and
a second logic inversion circuit associated with the second memory bank, an input node of the second logic inversion circuit being electrically coupled to the second memory bank to receive the respective second stored datum, the second logic inversion circuit being configured to output a respective second output datum by selecting either an inverted version of the respective second stored datum or a non-inverted version of the respective second stored datum for all of the second plurality of memory cells based on the second column of the second memory bank.
3 . The circuit of claim 1 , wherein the memory output block further includes:
a plurality of memory banks, the plurality of memory banks including the first memory bank, each memory bank of the plurality of memory banks having a respective plurality of columns, wherein each column of the respective plurality of columns has a plurality of memory cells, each memory cell of the plurality of memory cells of each column of the respective plurality of columns being configured to store a respective stored datum; and
a plurality of logic inversion circuits, the plurality of logic inversion circuits including the first logic inversion circuit, each logic inversion circuit of the plurality of logic inversion circuits being associated with a respective one memory bank of the plurality of memory banks, an input node of the respective logic inversion circuit being electrically coupled to the respective one memory bank to receive the respective stored datum, each logic inversion circuit of the plurality of logic inversion circuits being configured to output a respective output datum by selecting either an inverted version of the respective stored datum or a non-inverted version of the respective stored datum for all of the plurality of memory cells in a column of the respective plurality of columns based on the column of the respective plurality of columns.
4 . The circuit of claim 3 , wherein the memory output block further includes a buffer circuit, the logic inversion circuits being electrically connected to and configured to output the respective output datum to an input node of the buffer circuit, an output node of the buffer circuit being the single bit width output node of the memory output block.
5 . The circuit of claim 1 , wherein the first logic inversion circuit includes column inversion tag circuits, each column inversion tag circuit of the column inversion tag circuits being associated with a respective column of the first plurality of columns, a configuration of the respective column inversion tag circuit determining whether the first logic inversion circuit selects the inverted version of a respective stored datum or the non-inverted version of the respective stored datum for all of a plurality of memory cells in the respective column of the first plurality of columns based on the respective column of the first plurality of columns.
6 . The circuit of claim 1 , wherein the first logic inversion circuit includes:
a sense amplifier having an input node electrically coupled to the first memory bank;
an inverter having an input node electrically connected to an output node of the sense amplifier;
a multiplexer having a first input node electrically connected to the output node of the sense amplifier and having a second input node electrically connected to an output node of the inverter; and
column inversion tag circuits, each column inversion tag circuit of the column inversion tag circuits being associated with a respective column of the first plurality of columns, each column inversion tag circuit of the column inversion tag circuits including:
a pull-down transistor having a drain node electrically connected to a data inversion control node of the respective column inversion tag circuit, the data inversion control node being electrically connected to a selection input node of the multiplexer; and
a pull-up transistor having a drain node electrically connected to the data inversion control node of the respective column inversion tag circuit, wherein either the pull-down transistor is disabled from pulling down a voltage of the data inversion control node or the pull-up transistor is disabled from pulling up the voltage of the data inversion control node, wherein whether the pull-down transistor is disabled or the pull-up transistor is disabled determines whether the first logic inversion circuit selects the inverted version of a respective stored datum or the non-inverted version of the respective stored datum for all of a plurality of memory cells in the respective column of the first plurality of columns with which the respective column inversion tag is associated.
7 . The circuit of claim 1 , wherein the first logic inversion circuit includes:
a sense amplifier having an input node electrically coupled to the first memory bank;
an inverter having an input node electrically connected to an output node of the sense amplifier;
a multiplexer having a first input node electrically connected to the output node of the sense amplifier and having a second input node electrically connected to an output node of the inverter;
column inversion tag circuits, each column inversion tag circuit of the column inversion tag circuits being associated with a respective column of the first plurality of columns, each column inversion tag circuit of the column inversion tag circuits including:
a pull-down transistor having a drain node electrically connected to an output node of the respective column inversion tag circuit, wherein whether a source node of the pull-down transistor is electrically floating or is electrically connected to a grounded power supply node determines whether the first logic inversion circuit selects the inverted version of a respective stored datum or the non-inverted version of the respective stored datum for all of a plurality of memory cells in the respective column of the first plurality of columns with which the respective column inversion tag is associated; and
a pull-up transistor having a drain node electrically connected to the output node of the respective column inversion tag circuit and having a source node electrically connected to a positive power supply node; and
a combinational logic circuit having input nodes electrically connected to the respective output nodes of the column inversion tag circuits, an output node of the combinational logic circuit being electrically connected to a selection input node of the multiplexer.
8 . A method comprising:
reading a stored datum from a memory cell in a column of a memory bank, the memory bank having a plurality of columns including the column, wherein the column has a plurality of memory cells including the memory cell, each memory cell of the plurality of memory cells being configured to store a respective stored datum; and
outputting an output datum from a logic inversion circuit electrically coupled to the memory bank comprising selecting either one of an inverted version of the respective stored datum or a non-inverted version of the respective stored datum for all of the plurality of memory cells based on the column of the memory bank.
9 . The method of claim 8 , wherein the memory bank is included in a memory block having a single bit width output node, the memory block including a plurality of memory banks, the plurality of memory banks including the memory bank.
10 . The method of claim 9 , further comprising outputting the output datum from a buffer circuit, the memory block including a plurality of logic inversion circuits, the plurality of logic inversion circuits including the logic inversion circuit, each logic inversion circuit of the plurality of logic inversion circuits being associated with a respective memory bank of the plurality of memory banks, the buffer circuit having an input node electrically connected to output nodes of the plurality of logic inversion circuits, the output datum being output on the output node of the logic inversion circuit.
11 . The method of claim 8 , wherein the logic inversion circuit includes column inversion tag circuits corresponding to respective columns of the plurality of columns, a column inversion tag circuit of the column inversion tag circuits corresponding the column of the plurality of columns from which the stored datum is read indicating whether to select the inverted version of the stored datum to obtain the output datum, the logic inversion circuit selecting the inverted version of the stored datum to obtain the output datum when the column inversion tag circuit indicates that the inverted version of the stored datum is to be selected, the logic inversion circuit selecting the non-inverted version of the stored datum to obtain the output datum when the column inversion tag circuit indicates that the non-inverted version of the stored datum is to be selected.
12 . The method of claim 8 , wherein the logic inversion circuit includes:
a sense amplifier having an input node receiving the stored datum from the memory bank;
an inverter having an input node electrically connected to an output node of the sense amplifier;
a multiplexer having a first input node electrically connected to the output node of the sense amplifier and having a second input node electrically connected to an output node of the inverter, the non-inverted version of the stored datum being on the first input node of the multiplexer, the inverted version of the stored datum being on the second input node of the multiplexer; and
column inversion tag circuits corresponding to respective columns of the plurality of columns, the column inversion tag circuits controlling a voltage on a selection input node of the multiplexer to select the inverted version of the stored datum or the non-inverted version of the stored datum to obtain the output datum.
13 . The method of claim 12 , wherein each column inversion tag circuit of the column inversion tag circuits includes:
a pull-down transistor having a drain node electrically connected to a data inversion control node of the respective column inversion tag circuit, the data inversion control node being electrically connected to the selection input node of the multiplexer; and
a pull-up transistor having a drain node electrically connected to the data inversion control node of the respective column inversion tag circuit, wherein either the pull-down transistor is disabled from pulling down a voltage of the data inversion control node or the pull-up transistor is disabled from pulling up the voltage of the data inversion control node, wherein whether the pull-down transistor is disabled or the pull-up transistor is disabled determines whether the logic inversion circuit selects the inverted version of the stored datum or the non-inverted version of the stored datum when the stored datum is read from the column of the plurality of columns corresponding to the respective column inversion tag circuit.
14 . The method of claim 12 , wherein:
each column inversion tag circuit of the column inversion tag circuits includes:
a pull-down transistor having a drain node electrically connected to an output node of the respective column inversion tag circuit, wherein whether a source node of the pull-down transistor is electrically floating or is electrically connected to a grounded power supply node determines whether the logic inversion circuit selects the inverted version of the stored datum or the non-inverted version of the stored datum when the stored datum is read from the column of the plurality of columns corresponding to the respective column inversion tag circuit; and
a pull-up transistor having a drain node electrically connected to the output node of the respective column inversion tag circuit and having a source node electrically connected to a positive power supply node; and
the logic inversion circuit includes a combinational logic circuit having input nodes electrically connected to respective output nodes of the column inversion tag circuits, an output node of the combinational logic circuit being electrically connected to the selection input node of the multiplexer.
15 . A non-transitory computer-readable storage medium storing an electronic representation of a circuit design, the circuit design comprising:
a logic inversion circuit configured to receive on an input node a read datum from a memory bank, the logic inversion circuit comprising column inversion tag circuits, each column inversion tag circuit of the column inversion tag circuits corresponding to a respective column of the memory bank and being configurable to indicate whether to select an inverted version of the read datum or a non-inverted version of the read datum, the logic inversion circuit being configured to obtain an output datum for outputting on an output node of the logic inversion circuit by selecting the inverted version of the read datum or the non-inverted version of the read datum based on a configuration of the respective column inversion tag circuit corresponding to the respective column of the memory bank from which the read datum is read.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein each column inversion tag circuit of the column inversion tag circuits includes:
a pull-down transistor; and
a pull-up transistor, a drain node of the pull-down transistor being electrically connected to a drain node of the pull-up transistor, wherein the respective column inversion tag circuit is configurable to indicate whether to select the inverted version of the read datum or the non-inverted version of the read datum by selectively electrically connecting either of a source node of the pull-down transistor to a grounded power supply node or a source node of the pull-up transistor to a positive power supply node.
17 . The non-transitory computer-readable storage medium of claim 15 , wherein each column inversion tag circuit of the column inversion tag circuits includes:
a pull-down transistor, wherein the respective column inversion tag circuit is configurable to indicate whether to select the inverted version of the read datum or the non-inverted version of the read datum by selectively electrically connecting a source node of the pull-down transistor to a grounded power supply node; and
a pull-up transistor, a drain node of the pull-down transistor being electrically connected to a drain node of the pull-up transistor, a source node of the pull-up transistor being electrically connected to a positive power supply node.
18 . The non-transitory computer-readable storage medium of claim 15 , wherein each column inversion tag circuit of the column inversion tag circuits is configurable to indicate whether to select the inverted version of the read datum or the non-inverted version of the read datum by selectively inserting one or more metal vias in a layout of the respective column inversion tag circuit.
19 . The non-transitory computer-readable storage medium of claim 15 , wherein the circuit design further comprises:
a sense amplifier having an input node that is electrically connected to the input node of the logic inversion circuit;
an inverter having an input node electrically connected to an output node of the sense amplifier; and
a multiplexer having a first input node electrically connected to the output node of the sense amplifier and having a second input node electrically connected to an output node of the inverter, the column inversion tag circuits being configured to control a signal on a selection input node of the multiplexer.
20 . The non-transitory computer-readable storage medium of claim 15 , wherein the circuit design further comprises the memory bank the memory bank being electrically coupled to the input node of the logic inversion circuit, the memory bank comprising memory cells arranged in columns, the memory cells being configurable to store respective data.