Incremental synthesis from RTL circuit designs in EDA
A method for incremental synthesis of a changed RTL design. A current RTL design and an implementation of a previous RTL design are processed to generate reuse information identifying one or more reusable design entities of the implementation of the previous register-transfer level design. An implementation of the current RTL design is generated by processing design entities of the current RTL design to generate synthesized logic corresponding to the design entities of the current RTL design, and combining the one or more reusable design entities with the synthesized logic based on the reuse information.
1 . A system comprising:
one or more hardware processors; and
a computer-readable storage medium storing instructions, which when executed by the one or more processors, cause the system to perform operations comprising:
accessing, by the one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design; and
generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design; and
combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.
2 . The system of claim 1 , wherein:
combining the one or more reusable design entities with the synthesized logic based on the reuse information comprises:
generating an engineering change order patch based on the reuse information and the synthesized logic using a conformal engineering change order; and
applying the engineering change order patch to the implementation of the previous register-transfer level design.
3 . The system of claim 1 , wherein:
the current register-transfer level design comprises register-transfer level design data comprising hardware description language data.
4 . The system of claim 1 , wherein:
the reuse information comprises design content match information identifying the one or more reusable design entities as satisfying a content matching condition; and
the content matching condition requires that a design entity of the previous register-transfer level design has register-transfer level content matching register-transfer level content of one or more corresponding design entities of the current register-transfer level design.
5 . The system of claim 4 , wherein:
generating the reuse information comprises:
generating current design content information representative of register-transfer level content of the plurality of design entities of the current register-transfer level design;
obtaining previous design content information representative of register-transfer level content of each design entity of the previous register-transfer level design corresponding to a design entity of the current register-transfer level design;
comparing the current design content information to the previous design content information to generate the design content match information; and
selecting the one or more reusable design entities based on the design content match information.
6 . The system of claim 5 , wherein:
the current design content information comprises a hash value for each design entity of the current register-transfer level design; and
the previous design content information comprises a hash value for each design entity of the previous register-transfer level design.
7 . The system of claim 6 , wherein:
a hash value for an individual design entity of at least one of the current register-transfer level design or the previous register-transfer level design is generated by:
obtaining register-transfer level entity data representative of the individual design entity;
normalizing non-register-transfer level content of the register-transfer level entity data representative of the individual design entity to generate a normalized representation of the design entity; and
generating the hash value based on the normalized representation of the individual design entity.
8 . The system of claim 5 , wherein:
the reuse information further comprises boundary optimization information identifying one or more boundary changes between the previous register-transfer level design and the current register-transfer level design.
9 . The system of claim 8 , wherein:
the reuse information further comprises hierarchy information representative of one or more parent-child relationships between the design entities of the previous register-transfer level design.
10 . The system of claim 9 , wherein:
selecting the one or more reusable design entities further comprises:
processing the boundary optimization information to determine that the one or more reusable design entities satisfy a boundary optimization condition.
11 . The system of claim 10 , wherein:
a design entity satisfies the boundary optimization condition if the design entity has no boundary changes that are any of the following: a Boolean satisfiability change across a boundary of the design entity, a binary decision diagram change across a boundary of the design entity, or a push feedthrough change outside the design entity.
12 . The system of claim 11 , wherein:
selecting the one or more reusable design entities further comprises:
processing the boundary optimization information and the hierarchy information to determine that the one or more reusable design entities satisfy a hierarchical boundary condition, wherein:
the hierarchical boundary condition requires that any children of a design entity either satisfy the content matching condition or satisfy the boundary optimization condition.
13 . The system of claim 12 , wherein:
the hierarchical boundary condition further requires that a design entity have no child that fails to satisfy the hierarchical boundary condition and also fails to satisfy the boundary optimization condition.
14 . The system of claim 13 , wherein:
selecting the one or more reusable design entities further comprises:
treating any design entity with re-timing enabled as failing to satisfy the content matching condition and failing to satisfy the boundary optimization condition.
15 . A method comprising:
accessing, by one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design; and
generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design; and
combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.
16 . The method of claim 15 , wherein:
the reuse information comprises design content match information identifying the one or more reusable design entities as satisfying a content matching condition; and
the content matching condition requires that a design entity of the previous register-transfer level design has register-transfer level content matching register-transfer level content of one or more corresponding design entities of the current register-transfer level design.
17 . The method of claim 16 , wherein:
generating the reuse information comprises:
generating current design content information representative of register-transfer level content of the plurality of design entities of the current register-transfer level design;
obtaining previous design content information representative of register-transfer level content of each design entity of the previous register-transfer level design corresponding to a design entity of the current register-transfer level design;
comparing the current design content information to the previous design content information to generate the design content match information; and
selecting the one or more reusable design entities based on the design content match information.
18 . The method of claim 17 , wherein:
the reuse information further comprises boundary optimization information identifying one or more boundary changes between the previous register-transfer level design and the current register-transfer level design; and
selecting the one or more reusable design entities further comprises:
processing the boundary optimization information to determine that the one or more reusable design entities satisfy a boundary optimization condition.
19 . The method of claim 18 , wherein:
the reuse information further comprises hierarchy information representative of one or more parent-child relationships between the design entities of the previous register-transfer level design; and
selecting the one or more reusable design entities further comprises:
processing the boundary optimization information and the hierarchy information to determine that the one or more reusable design entities satisfy a hierarchical boundary condition, wherein:
the hierarchical boundary condition requires that any children of a design entity either satisfy the content matching condition or satisfy the boundary optimization condition.
20 . A non-transitory computer-readable storage medium, the computer-readable storage medium comprising instructions that when executed by one or more hardware processors of a system, cause the system to perform operations comprising:
accessing, by the one or more hardware processors, a current register-transfer level design that comprises a plurality of design entities defined at a register-transfer level;
accessing, by the one or more hardware processors, an implementation of a previous register-transfer level design that comprises a plurality of design entities defined at an implementation level;
processing, by the one or more hardware processors, the current register-transfer level design and the implementation of the previous register-transfer level design to generate reuse information that identifies one or more reusable design entities, the one or more reusable design entities comprising design entities of the implementation of the previous register-transfer level design that can be reused in implementing the current register-transfer level design; and
generating, by the one or more hardware processors, an implementation of the current register-transfer level design by:
processing one or more design entities of the current register-transfer level design to generate synthesized logic corresponding to the one or more design entities of the current register-transfer level design; and
combining the one or more reusable design entities with the synthesized logic based on the reuse information to generate the implementation of the current register-transfer level design.