Display panel and display apparatus
The present application discloses a display panel and a display apparatus. The display panel includes a first driving circuit, the first driving circuit including a plurality of stages of shift register. The shift register includes: a first shift control module electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node; a second shift control module electrically connected the input terminal, the first clock terminal, the first node, a second power supply terminal, and a fourth node; a shift output module electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and a shift output terminal; and a potential control module electrically connected to the third node, a second clock terminal, and the second node.
1 . A display panel comprising a first driving circuit comprising a plurality of stages of shift registers, each of the shift registers comprising:
a first shift control module electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node, the first shift control module being configured to control a signal of the first node, a signal of the second node, and a signal of the third node;
a second shift control module electrically connected to the input terminal, the first clock terminal, the first node, a second power supply terminal, and a fourth node, the second shift control module being configured to control a signal of the fourth node;
a shift output module electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and a shift output terminal, the shift output module being configured to control the shift output terminal to output a shift signal;
a potential control module electrically connected to the third node, a second clock terminal, and the second node, the potential control module being configured to control the signal of the second node; and
a refresh output section comprising a scan output terminal, the refresh output section being electrically connected to a first refresh signal line and configured to control the scan output terminal to output a gate drive signal.
2 . The display panel according to claim 1 , wherein the potential control module comprises:
a first potential control sub-module electrically connected to the second clock terminal and the third node, the first potential control sub-module being configured to control the signal of the third node; and
a second potential control sub-module electrically connected to the third node and the second node, the second potential control sub-module being configured to control the signal of the second node.
3 . The display panel according to claim 2 , wherein the first potential control sub-module comprises:
a first potential control unit electrically connected to the second clock terminal, the third node, and a fifth node, the first potential control unit being configured to control a signal of the fifth node; and
a first coupling unit, a first terminal of the first coupling unit being electrically connected to the fifth node, and a second terminal of the first coupling unit being electrically connected to the third node.
4 . The display panel according to claim 3 , wherein the first potential control unit comprises a first transistor, a gate of the first transistor being electrically connected to the third node, a first terminal of the first transistor being electrically connected to the second clock terminal, and a second terminal of the first transistor being electrically connected to the fifth node.
5 . The display panel according to claim 3 , wherein the first coupling unit comprises a first capacitor, a first plate of the first capacitor being electrically connected to the fifth node, and a second plate of the first capacitor being electrically connected to the third node.
6 . The display panel according to claim 1 , wherein a phase of a first clock signal provided by the first clock terminal is different from a phase of a second clock signal provided by the second clock terminal.
7 . The display panel according to claim 6 , wherein a period of the first clock signal is equal to a period of the second clock signal.
8 . The display panel according to claim 7 , wherein a phase difference between the first clock signal and the second clock signal is 2/H, where H is the period of the first clock signal.
9 . The display panel according to claim 3 , wherein the first potential control sub-module comprises a second potential control unit electrically connected to the fourth node, a third power supply terminal, and the fifth node, the second potential control unit being configured to control the signal of the fifth node.
10 . The display panel according to claim 9 , wherein the second potential control unit comprises a second transistor, a gate of the second transistor being electrically connected to the fourth node, a first terminal of the second transistor being electrically connected to the third power supply terminal, and a second terminal of the second transistor being electrically connected to the fifth node.
11 . The display panel according to claim 9 , wherein a third power supply signal provided by the third power supply terminal is a fixed voltage signal.
12 . The display panel according to claim 11 , wherein the second power supply signal provided by the second power supply terminal is the same as the third power supply signal.
13 . The display panel according to claim 2 , wherein the second potential control sub-module comprises a third transistor, a gate and a first terminal of the third transistor each being connected to the third node, and a second terminal of the third transistor being electrically connected to the second node.
14 . The display panel according to claim 1 , wherein the first shift control module comprises:
a first shift control sub-module electrically connected to the input terminal, the first clock terminal, the first power supply terminal, the first node, and the second node, the first shift control sub-module being configured to control the signal of the first node and the signal of the second node; and
a second shift control sub-module electrically connected to the input terminal, the first clock terminal, the first power supply terminal, and the third node, the second shift control sub-module being configured to control the signal of the third node;
wherein the first shift control sub-module comprises:
a fourth transistor, a gate of the fourth transistor being electrically connected to the first clock terminal, a first terminal of the fourth transistor being electrically connected to the input terminal, and a second terminal of the fourth transistor being electrically connected to the first node; and
a fifth transistor, a gate of the fifth transistor being electrically connected to the first power supply terminal, a first terminal of the fifth transistor being electrically connected to the first node, and a second terminal of the fifth transistor being electrically connected to the second node;
wherein the second shift control sub-module comprises:
a sixth transistor, a gate of the sixth transistor being electrically connected to the first clock terminal, a first terminal of the sixth transistor being electrically connected to the input terminal, and a second terminal of the sixth transistor being electrically connected to a first terminal of a seventh transistor; and
the seventh transistor, a gate of the seventh transistor being electrically connected to the first power supply terminal, and a second terminal of the seventh transistor being electrically connected to the third node.
15 . The display panel according to claim 1 , wherein the second shift control module comprises:
a third shift control sub-module electrically connected to the input terminal, the second power supply terminal, and a sixth node, the third shift control sub-module being configured to control a signal of the sixth node; and
a fourth shift control sub-module electrically connected to the sixth node, the first clock terminal, the second power supply terminal, the first node, and the fourth node, the fourth shift control sub-module being configured to control the signal of the fourth node;
wherein the third shift control sub-module comprises an eighth transistor, a gate of the eighth transistor being electrically connected to the input terminal, a first terminal of the eighth transistor being electrically connected to the second power supply terminal, and a second terminal of the eighth transistor being electrically connected to the sixth node;
wherein the fourth shift control sub-module comprises:
a ninth transistor, a gate of the ninth transistor being electrically connected to the sixth node, a first terminal of the ninth transistor being electrically connected to the first clock terminal, and a second terminal of the ninth transistor being electrically connected to the fourth node; and
a tenth transistor, a gate of the tenth transistor being electrically connected to the first node, a first terminal of the tenth transistor being electrically connected to the second power supply terminal, and a second terminal of the tenth transistor being electrically connected to the fourth node;
wherein the fourth shift control sub-module comprises a second capacitor, a first plate of the second capacitor being electrically connected to the sixth node, and a second plate of the second capacitor being electrically connected to the first clock terminal.
16 . The display panel according to claim 1 , wherein the shift output module comprises:
a first output sub-module electrically connected to the fourth node, the second power supply terminal, and the shift output terminal, the first output sub-module being configured to control the shift output terminal to output the shift signal; and
a second output sub-module electrically connected to the second node, the first power supply terminal, and the shift output terminal, the second output sub-module being configured to control the shift output terminal to output the shift signal.
17 . The display panel according to claim 16 , wherein the first output sub-module comprises:
an eleventh transistor, a gate of the eleventh transistor being electrically connected to the fourth node, a first terminal of the eleventh transistor being electrically connected to the second power supply terminal, and a second terminal of the eleventh transistor being electrically connected to the shift output terminal; and
a third capacitor, a first plate of the third capacitor being electrically connected to the fourth node, and a second plate of the third capacitor being electrically connected to the second power supply terminal.
18 . The display panel according to claim 17 , wherein the second output sub-module comprises a twelfth transistor, a gate of the twelfth transistor being electrically connected to the second node, a first terminal of the twelfth transistor being electrically connected to the first power supply terminal, and a second terminal of the twelfth transistor being electrically connected to the shift output terminal;
wherein the second output sub-module comprises a fourth capacitor, a first plate of the fourth capacitor being electrically connected to the second node, and a second plate of the fourth capacitor being electrically connected to the shift output terminal.
19 . The display panel according to claim 1 , wherein an operation process of the shift register comprises
a first stage, in which a transmission path between the first power supply terminal and the shift output terminal in the shift output module is controlled to be conductive, so that a first power supply signal provided by the first power supply terminal is transmitted to the shift output terminal; and
a second stage, in which a transmission path between the second power supply terminal and the shift output terminal in the shift output module is controlled to be conductive, so that a second power supply signal provided by the second power supply terminal is transmitted to the shift output terminal;
wherein the second clock signal provided by the second clock terminal toggles between a first level signal and a second level signal;
in the first stage, under a condition that the second clock signal toggles to the first level signal, the potential control module is controlled to be turned on, and under a condition that the second clock signal toggles to the second level signal, the potential control module is controlled to be turned off, the first level signal has a same polarity as the signal of the second node, and the second level signal has an opposite polarity to the signal of the second node; and
in the second stage, the potential control module is turned off.
20 . A display apparatus, comprising a display panel which comprises a first driving circuit, the first driving circuit comprising a plurality of stages of shift registers, each of the shift registers comprising:
a first shift control module electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node, the first shift control module being configured to control a signal of the first node, a signal of the second node, and a signal of the third node;
a second shift control module electrically connected to the input terminal, the first clock terminal, the first node, a second power supply terminal, and a fourth node, the second shift control module being configured to control a signal of the fourth node;
a shift output module electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and a shift output terminal, the shift output module being configured to control the shift output terminal to output a shift signal;
a potential control module electrically connected to the third node, a second clock terminal, and the second node, the potential control module being configured to control the signal of the second node; and
a refresh output section comprising a scan output terminal, the refresh output section being electrically connected to a first refresh signal line and configured to control the scan output terminal to output a gate drive signal.