Analog front end of receiver for high baud-rate communications
In an analog front end (AFE) for a communication receiver, an input matching network is configured to receive a differential input signal. One or more first buffer amplifiers are coupled to the input matching network. A sampler array is coupled to the one or more first buffer amplifiers. The sampler array includes a plurality of instances of track and hold circuitry, each instance of the track and hold circuitry configured to generate an analog output signal. A plurality of second buffer amplifiers are coupled to the sampler array. Each second buffer amplifier comprises respective super source follower (SSF) circuitry and is configured to amplify a respective analog output signal of the sampler array.
1 . Analog front end (AFE) circuitry for a communication receiver, the AFE circuitry comprising:
an input matching network configured to receive a differential input signal;
one or more first buffer amplifiers coupled to the input matching network;
a sampler array coupled to the one or more first buffer amplifiers, the sampler array comprising a plurality of instances of track and hold circuitry, each instance of the track and hold circuitry configured to generate an analog output signal; and
a plurality of second buffer amplifiers coupled to the sampler array, each second buffer amplifier comprising respective super source follower (SSF) circuitry and being configured to amplify a respective analog output signal of the sampler array, and each SSF circuitry of each second buffer amplifier comprising:
a first transistor having a first gate coupled to a first differential input node of the second buffer amplifier;
a second transistor having a second gate coupled to a second differential input node of the second buffer amplifier;
first feedback circuitry that is coupled to a first drain of the first transistor, the first feedback circuitry comprising a first resistor in parallel with a first capacitor, the first resistor and the first capacitor coupling the first drain of the first transistor to a voltage supply;
second feedback circuitry that is coupled to a second drain of the second transistor, the second feedback circuitry comprising a second resistor in parallel with a second capacitor, the second resistor and the second capacitor coupling the second drain of the second transistor to the voltage supply;
a third transistor coupled in series with the first transistor, the third transistor having i) a third drain coupled to a first source of the first transistor, and ii) a third gate coupled to the second differential input node of the second buffer amplifier; and
a fourth transistor coupled in series with the first transistor and the third transistor, the third transistor being coupled between the first transistor and the fourth transistor, the fourth transistor having a fourth source coupled to ground and a fourth drain coupled to a third source of the third transistor.
2 . The AFE circuitry of claim 1 , wherein:
each SSF circuitry of each second buffer amplifier further comprises a fifth transistor having a fifth drain coupled to a second source of the second transistor;
the first feedback circuitry of each SSF circuitry further comprises a third capacitor coupled between the first drain of the first transistor and a fourth gate of the fifth transistor; and
the second feedback circuitry of each SSF circuitry further comprises a fourth capacitor coupled between the second drain of the second transistor and a fifth gate of the fifth transistor.
3 . The AFE circuitry of claim 1 , wherein:
the first feedback circuitry of each SSF circuitry comprises a first third capacitor coupled between the first drain of the first transistor and the second gate of the second transistor; and
the second feedback circuitry of each SSF circuitry comprises a second-fourth capacitor coupled between the second drain of the second transistor and the first gate of the first transistor.
4 . The AFE circuitry of claim 1 , wherein the third transistor and the fourth transistor of each SSF circuitry of each second buffer amplifier corresponds to:
common source circuitry of each SSF circuitry of each second buffer amplifier, the common source circuitry coupled to the first source of the first transistor and the second differential input node.
5 . The AFE circuitry of claim 1 , wherein common source circuitry of each SSF circuitry comprises:
a fifth transistor having i) a fifth drain coupled to the second source of the second transistor, and ii) a fifth gate coupled to the first differential input node of the second buffer amplifier; and
a sixth transistor having a sixth source coupled to ground and a sixth drain coupled to a fifth source of the fifth transistor.
6 . The AFE circuitry of claim 1 , wherein each SSF circuitry of each second buffer amplifier comprises:
a fifth transistor having i) a fifth drain coupled to the first source of the first transistor, ii) a fifth source coupled to a second source of the second transistor, and iii) a fifth gate coupled to a first calibration voltage, the fifth transistor being configured to adjust a gain of the SSF circuitry based on the first calibration voltage.
7 . The AFE circuitry of claim 6 , wherein each SSF circuitry of each second buffer amplifier further comprises:
a sixth transistor having i) a sixth drain coupled to the first drain of the first transistor, ii) a sixth source coupled to the second drain of the second transistor, and iii) a sixth gate coupled to a second calibration voltage, the sixth transistor being configured to further adjust the gain of the SSF circuitry based on the second calibration voltage.
8 . The AFE circuitry of claim 1 , wherein the AFE comprises a plurality of first buffer amplifiers, and wherein each first buffer amplifier comprises a class AB buffer amplifier that includes:
a first NMOS transistor having a source and a drain;
a first PMOS transistor having a source coupled to the source of the first NMOS transistor;
a second NMOS transistor having a source and a drain;
a second PMOS transistor having a source coupled to the source of the second NMOS transistor;
third feedback circuitry coupled between the source of the first NMOS transistor and the drain of the second NMOS transistor, and coupled between the source of the second NMOS transistor and the drain of the first NMOS transistor; and
fourth feedback circuitry coupled between the source of the first PMOS transistor and a drain of the second PMOS transistor, and coupled between the source of the second PMOS transistor and a drain of the first PMOS transistor.
9 . The AFE circuitry of claim 8 , wherein:
each third feedback circuitry of each first buffer amplifier comprises i) a first impedance coupled between a voltage supply and the drain of the first NMOS transistor, and ii) a second impedance coupled between the voltage supply and the drain of the second NMOS transistor; and
each fourth feedback circuitry of each first buffer amplifier comprises i) a third impedance coupled between ground and the drain of the first PMOS transistor, and ii) a fourth impedance coupled between ground and the drain of the second PMOS transistor.
10 . The AFE circuitry of claim 1 , wherein the input matching network comprises:
a first T-coil circuit;
a second T-coil circuit;
a first impedance coupled between the first T-coil circuit and a first input node of the input matching network; and
a second impedance coupled between the second T-coil circuit and a second input node of the input matching network;
wherein the first impedance and the second impedance are configured to shift a portion of input loss of the impedance matching network to a frequency above a signaling frequency corresponding to the AFE.
11 . The AFE circuitry of claim 10 , wherein the input matching network further comprises:
a first resistor coupled to the first T-coil circuit;
a second resistor coupled between the first resistor and ground;
a third resistor coupled to the second T-coil circuit;
a fourth resistor coupled between the third resistor and ground; and
a shunt capacitor coupled between the first resistor and the third resistor.
12 . Analog front end (AFE) circuitry for a communication receiver, the AFE circuitry comprising:
an input matching network configured to receive a differential input signal;
a plurality of first buffer amplifiers coupled to the input matching network, each first buffer amplifier comprising a class AB source follower buffer amplifier that includes:
a first NMOS transistor having a source and a drain,
a first PMOS transistor having a source coupled to the source of the first NMOS transistor,
a second NMOS transistor having a source and a drain,
a second PMOS transistor having a source coupled to the source of the second NMOS transistor,
a first differential output node between the first NMOS transistor and the first PMOS transistor, the first differential output node connected to the source of the first NMOS transistor,
a second differential output node between the second NMOS transistor and the second PMOS transistor, the second differential output node connected to the source of the second NMOS transistor,
first feedback circuitry coupled between the source of the first NMOS transistor and the drain of the second NMOS transistor, and coupled between the source of the second NMOS transistor and the drain of the first NMOS transistor, and
second feedback circuitry coupled between the source of the first PMOS transistor and a drain of the second PMOS transistor, and coupled between the source of the second PMOS transistor and a drain of the first PMOS transistor;
a sampler array coupled to the plurality of first buffer amplifiers, the sampler array comprising a plurality of instances of track and hold circuitry, each instance of the track and hold circuitry configured to generate an analog output signal; and
a plurality of second buffer amplifiers coupled to the sampler array, each second buffer amplifier being configured to amplify a respective analog output signal of the sampler array.
13 . The AFE circuitry of claim 12 , wherein:
each first feedback circuitry of each first buffer amplifier comprises i) a first impedance coupled between a voltage supply and the drain of the first NMOS transistor, and ii) a second impedance coupled between the voltage supply and the drain of the second NMOS transistor; and
each second feedback circuitry of each first buffer amplifier comprises i) a third impedance coupled between ground and the drain of the first PMOS transistor, and ii) a fourth impedance coupled between ground and the drain of the second PMOS transistor.
14 . The AFE circuitry of claim 12 , wherein the input matching network comprises:
a first T-coil circuit;
a second T-coil circuit;
a first impedance coupled between the first T-coil circuit and a first input node of the input matching network; and
a second impedance coupled between the second T-coil circuit and a second input node of the input matching network;
wherein the first impedance and the second impedance are configured to shift a portion of input loss of the impedance matching network to a frequency above a signaling frequency corresponding to the AFE.
15 . The AFE circuitry of claim 14 , wherein the input matching network further comprises:
a first resistor coupled to the first T-coil circuit;
a second resistor coupled between the first resistor and ground;
a third resistor coupled to the second T-coil circuit;
a fourth resistor coupled between the third resistor and ground; and
a shunt capacitor coupled between the first resistor and the third resistor.
16 . Analog front end (AFE) circuitry for a communication receiver, the AFE circuitry comprising:
an input matching network configured to receive a differential input signal, including:
a first T-coil circuit,
a second T-coil circuit,
a first impedance coupled between the first T-coil circuit and a first input node of the input matching network, the first impedance comprising a first inductor coupled in series between the first T-coil circuit and the first input node of the input matching network, and
a second impedance coupled between the second T-coil circuit and a second input node of the input matching network, the second impedance comprising a second inductor coupled in series between the second T-coil circuit and the second input node of the input matching network, the first impedance and the second impedance being configured to shift a portion of input loss of the impedance matching network to a frequency above a signaling frequency corresponding to the AFE;
one or more first buffer amplifiers coupled to the input matching network;
a sampler array coupled to the one or more first buffer amplifiers, the sampler array comprising a plurality of instances of track and hold circuitry, each instance of the track and hold circuitry configured to generate an analog output signal; and
a plurality of second buffer amplifiers coupled to the sampler array, each second buffer amplifier comprising respective super source follower (SSF) circuitry and being configured to amplify a respective analog output signal of the sampler array.
17 . The AFE circuitry of claim 16 , wherein the input matching network further comprises:
a first resistor coupled to the first T-coil circuit;
a second resistor coupled between the first resistor and ground;
a third resistor coupled to the second T-coil circuit;
a fourth resistor coupled between the third resistor and ground; and
a shunt capacitor coupled between the first resistor and the third resistor.
18 . The AFE circuitry of claim 16 , wherein:
the first impedance further comprises a first resistor coupled in parallel with the first inductor; and
the second impedance further comprises a second resistor coupled in parallel with the second inductor.