IP Library › Granted Patent US 12,750,062
Granted Patent B1
US 12,750,062 · App. 19/357,233 · Granted Sep 29, 2026

Simple self-disciplined oscillator

Inventor: Kiomars Anvari (Walnut Creek, CA)
Assignee: Kiomars Anvari
H03L7/187H03L7/0992
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Quick Facts
Patent No.
US 12,750,062
App. No.
19/357,233
Granted
Sep 29, 2026
Kind
B1
Abstract

A simple, and low-cost oscillator solution that uses a self-disciplined circuit to maintain its frequency with high accuracy. The self-disciplined circuit includes a counter and a constant delay circuit. The oscillator is used to increment the counter. The constant delay circuit records the value of the counter when triggers a delay block with a trigger signal and when the trigger signal is detected at the output of the delay block. The difference between the two counter values is used to calculate a time drift and to maintain the frequency of the oscillator at the desired value.

Claims (27)

1 . A simple self-adjusting oscillator (SSO) comprising:

an adjustable oscillator;

a control circuit; and

a desired operating frequency Fo;

said adjustable oscillator uses at least one of a voltage control oscillator (VCO), a voltage control crystal oscillator (VCXO), a voltage-controlled temperature compensated crystal oscillator (VC-TCXO), a temperature compensated crystal oscillator (TCXO), and an oven-controlled crystal oscillator (OCXO);

said control circuit consists of a counter that is incremented by said adjustable oscillator, an adjustment circuit, and a time delay circuit with a constant delay having a value D;

said time delay circuit sends a trigger signal to said constant delay and detects said trigger signal at the output of said constant delay;

said time delay circuit calculates a time drift of said adjustable oscillator by subtracting said value D from a difference of said counter's value Nd when said trigger signal is detected divided by said Fo and said counter's value Nt when said trigger signal is transmitted divided by said Fo which is said value D−(Nd−Nt)/Fo;

said time drift is used by said adjustment circuit to adjust said adjustable oscillator towards said Fo.

2 . The SSO of claim 1 , wherein said control circuit contains a configuration parameter.

3 . The SSO of claim 2 , wherein said time drift is modified by said adjustment circuit using said configuration parameter before adjusting said adjustable oscillator.

4 . The SSO of claim 3 , wherein said configuration parameter has a look up table containing information data of at least one of a temperature behavior of said constant delay, an aging behavior said constant delay, and a humidity behavior of said constant delay.

5 . The SSO of claim 2 , wherein said configuration parameter is a type of said constant delay.

6 . The SSO of claim 2 , wherein said configuration parameter is a bandwidth of said constant delay.

7 . The SSO of claim 2 , wherein said configuration parameter is an operating frequency of said constant delay.

8 . The SSO of claim 2 , wherein said configuration parameter is said trigger signal for said constant delay.

9 . The SSO of claim 2 , wherein said configuration parameter is said desired operating frequency for said adjustable oscillator.

10 . The SSO of claim 2 , wherein said configuration parameter is an accuracy requirement for said adjustable oscillator.

11 . The SSO of claim 2 , wherein said configuration parameter is an initial adjustment for said adjustable oscillator.

12 . The SSO of claim 2 , wherein said configuration parameter is an automatic frequency control (AFC) adjustment.

13 . The SSO of claim 1 , wherein said constant delay uses a delay block with said value D.

14 . The SSO of claim 13 , wherein said delay block delays said trigger signal.

15 . The SSO of claim 13 , wherein said constant delay is a plurality of said delay block in parallel or repeat triggering said delay block.

16 . The SSO of claim 13 , wherein said constant delay is a plurality of said delay block in series.

17 . The SSO of claim 1 , wherein said counter contains integer number.

18 . The SSO of claim 1 , wherein said adjustable oscillator is a phase lock loop circuit to produce said desired operating frequency Fo.

19 . The SSO of claim 1 , wherein said trigger signal is at least one of a pulse, an impulse, and a pattern.

Continuity (1)
Continuation In Part 19197531 · May 2, 2025
References Cited (6)
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