IP Library › Granted Patent US 4,161,417
Granted Patent Utility
US 4,161,417 · App. 05/842,683

Method of making CMOS structure with retarded electric field for minimum latch-up

Inventors: Ernest W. Yim, Paul G. G. VanLoon
Patented Case View Patent ↗
Granted: Jul 17, 1979 Filed: Oct 17, 1977
Inventors
Ernest W. Yim
Paul G. G. VanLoon
Assignee (at issue)
SILICONIX INCORPORATED

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Quick Facts
Patent No.
US 4,161,417
App. No.
05/842,683
Filed
1977-10-17
Granted
1979-07-17
Kind
A