IP Library › Granted Patent US 4,795,716
Granted Patent Utility
US 4,795,716 · App. 07/064,133

Method of making a power IC structure with enhancement and/or CMOS logic

Inventors: Hamza Yilmaz, Robert S. Wrathall, Mike F. Chang, Robert G. Hodgins
Patented Case View Patent ↗
Granted: Jan 3, 1989 Filed: Jun 19, 1987
Inventors
Hamza Yilmaz
Robert S. Wrathall
Mike F. Chang
Robert G. Hodgins
Assignee (at issue)
General Electric Company

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Quick Facts
Patent No.
US 4,795,716
App. No.
07/064,133
Filed
1987-06-19
Granted
1989-01-03
Kind
A