Granted Patent
Utility
US 4,853,562 · App. 07/112,925
Programmable logic array using single transistor to generate true or complement signal
Inventor:
Shitaka Yamada
Patented Case
View Patent ↗
Granted: Aug 1, 1989
Filed: Oct 27, 1987
Inventor
Shitaka Yamada
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.