Granted Patent
Utility
US 4,864,219 · App. 07/027,650
Method and apparatus for verifying proper placement of integrated circuits on circuit boards
Inventor:
Philip B. Parsons
Patented Case
View Patent ↗
Granted: Sep 5, 1989
Filed: Mar 19, 1987
Inventor
Philip B. Parsons
Assignee (at issue)
Genrad, Inc.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.