Granted Patent
Utility
US 5,185,875 · App. 07/302,839
Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
Inventors:
Kumar Chinnaswamy, Michael A. Gagliardo, John J. Lynch, James E. Tessari
Patented Case
View Patent ↗
Granted: Feb 9, 1993
Filed: Jan 27, 1989
Inventors
Kumar Chinnaswamy
Michael A. Gagliardo
John J. Lynch
James E. Tessari
Assignee (at issue)
Digital Equipment Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.