Granted Patent
Utility
US 5,290,717 · App. 07/896,571
Method of manufacturing semiconductor devices having a resist patern coincident with gate electrode
Inventor:
Katsuhiro Shimazu
Patented Case
View Patent ↗
Granted: Mar 1, 1994
Filed: Jun 10, 1992
Inventor
Katsuhiro Shimazu
Assignee (at issue)
Kawasaki Steel Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.