Granted Patent
Utility
US 5,309,371 · App. 07/543,549
Method of and apparatus for designing circuit block layout in integrated circuit
Inventors:
Hiromi Shikata, Yoshito Muraishi, Shoichi Moriya, Naoyasu Seki
Patented Case
View Patent ↗
Granted: May 3, 1994
Filed: Jun 26, 1990
Inventors
Hiromi Shikata
Yoshito Muraishi
Shoichi Moriya
Naoyasu Seki
Assignee (at issue)
Kawasaki Steel Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.