Granted Patent
Utility
US 5,436,912 · App. 07/983,866
Circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns
Inventor:
Bernhard Lustig
Patented Case
View Patent ↗
Granted: Jul 25, 1995
Filed: Mar 5, 1993
Inventor
Bernhard Lustig
Assignee (at issue)
Siemens Aktiengesellschaft
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.