Granted Patent
Utility
US 5,691,910 · App. 08/661,186
Generic gate level model for characterization of glitch power in logic cells
Inventor:
John A. Thodiyil
Patented Case
View Patent ↗
Granted: Nov 25, 1997
Filed: Jun 10, 1996
Inventor
John A. Thodiyil
Assignee (at issue)
LSI Logic Corporation
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.