Granted Patent
Utility
US 5,712,204 · App. 08/575,475
Method of making a semiconductor device having reduced junction capacitance between the source and drain regions and the substrate
Inventor:
Tadahiko Horiuchi
Patented Case
View Patent ↗
Granted: Jan 27, 1998
Filed: Dec 20, 1995
Inventor
Tadahiko Horiuchi
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.