Granted Patent
Utility
US 5,717,251 · App. 08/689,088
Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance
Inventors:
Yoshihiro Hayashi, Takahiro Onodera
Patented Case
View Patent ↗
Granted: Feb 10, 1998
Filed: Aug 5, 1996
Inventors
Yoshihiro Hayashi
Takahiro Onodera
Assignee (at issue)
NEC CORPORATION
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.