Granted Patent
Utility
US 5,744,964 · App. 08/686,391
Method and apparatus for electrical test of wiring patterns formed on a printed circuit board
Inventors:
Morishiro Sudo, Masaru Ishijima, Kazuo Yamazaki
Patented Case
View Patent ↗
Granted: Apr 28, 1998
Filed: Jul 25, 1996
Inventors
Morishiro Sudo
Masaru Ishijima
Kazuo Yamazaki
Assignee (at issue)
FUJITSU AUTOMATION LIMITED
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.