IP Library › Granted Patent US 5,774,480
Granted Patent Utility
US 5,774,480 · App. 08/541,660

Cyclic code check bits generation and error correction using sum of remainders

Inventor: John S. Willy
Patented Case View Patent ↗
Granted: Jun 30, 1998 Filed: Oct 10, 1995
Inventor
John S. Willy
Assignee (at issue)
Allied Telesyn International Corporation

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Quick Facts
Patent No.
US 5,774,480
App. No.
08/541,660
Filed
1995-10-10
Granted
1998-06-30
Kind
A