IP Library › Granted Patent US 5,892,370
Granted Patent Utility
US 5,892,370 · App. 08/781,985

Clock network for field programmable gate array

Inventors: David D. Eaton, Mukesh T. Lulla, Ker-Ching Liu
Patented Case View Patent ↗
Granted: Apr 6, 1999 Filed: Jan 3, 1997
Inventors
David D. Eaton
Mukesh T. Lulla
Ker-Ching Liu
Assignee (at issue)
QuickLogic Corporation

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Quick Facts
Patent No.
US 5,892,370
App. No.
08/781,985
Filed
1997-01-03
Granted
1999-04-06
Kind
A