Granted Patent
Utility
US 5,929,695 · App. 08/867,538
Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods
Inventors:
Tsiu C. Chan, Pervez Hassan Sagarwala
Patented Case
View Patent ↗
Granted: Jul 27, 1999
Filed: Jun 2, 1997
Inventors
Tsiu C. Chan
Pervez Hassan Sagarwala
Assignee (at issue)
STMICROELECTRONICS, INC.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.