Granted Patent
Utility
US 5,943,598 · App. 08/545,388
Integrated circuit with planarized dielectric layer between successive polysilicon layers
Inventor:
Yih-Shung Lin
Patented Case
View Patent ↗
Granted: Aug 24, 1999
Filed: Oct 19, 1995
Inventor
Yih-Shung Lin
Assignee (at issue)
STMICROELECTRONICS, INC.
This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.