IP Library › Granted Patent US 5,946,058
Granted Patent Utility
US 5,946,058 · App. 08/642,865

Transistor matrix device including features for minimizing the effect of parasitic capacitances

Inventors: Tsuyoshi Kamada, Yoji Nagase, Katsusige Asada
Patented Case View Patent ↗
Granted: Aug 31, 1999 Filed: May 6, 1996
Inventors
Tsuyoshi Kamada
Yoji Nagase
Katsusige Asada
Assignee (at issue)
Fujitsu Limited

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Quick Facts
Patent No.
US 5,946,058
App. No.
08/642,865
Filed
1996-05-06
Granted
1999-08-31
Kind
A